regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
3886 group user s manual
is revised. page 1-2; operating temperature range of is added. page 1-2; explanations of notes are partly revised. page 1-2; explanations of application are partly added. page 1-3; product name and note into figure 1 are partly added. page 1-3; note into figure 2 is added. page 1-4; figure 3 is added. page 1-5; figure 4 is partly revised. page 1-8; figure 5 is partly revised. page 1-9; explanations of packages are partly added. page 1-9; figure 6 is partly revised. page 1-9; table 3 is partly added. page 1-13; figure 9 is partly revised. page 1-14; notes into figure 10 are partly revised. page 1-16; related sfrs of p4 2 /int 0 /obf 00 , p4 3 /int 1 /obf 01 into table 6 are partly added. page 1-42; [port control register 2 (pctl2)] are added. page 1-46; explanations of bit 5 of [i 2 c clock control register (s2)] are partly revised. page 1-48; bit name of bit 4 of [i 2 c status register (s1)] is revised. page 1-49; bit name of bit 4 into figure 41 is revised. page 1-54; explanations of (3) restart condition generating procedure are partly revised. page 1-54; (6) stop condition input at 7th clock pulse is added. page 1-54; (7) es0 bit switch is added. page 1-55; figure 50 is partly revised. revision description list 3886 group user s manual (1/6) revision description
of cpu reprogramming mode operation procedure are partly eliminated. page 1-86; figure 83 is partly revised. page 1-89; explanations of a-d converter of notes on programming are partly eliminated. page 1-90; explanations of handling of power source pins of notes on usage are partly revised. page 1-90; erasing of flash memory version is added. revision description list 3886 group user s manual (2/6) revision description
3886 group user s manual (3/6) revision description
3886 group user s manual (4/6) revision description
3886 group user s manual (5/6) revision description
3886 group user s manual (6/6) revision description
3886 group. after reading this manual, the user should have a through knowledge of the functions and features of the 3886 group, and should be able to fully utilize the product. the manual starts with specifications and ends with application examples. for details of software, refer to the 740 family software manual. for details of development support tools, refer to the mitsubishi microcomputer development support tools homepage (http://www.tool-spt.mesc.co.jp/index_e.htm).
3886 group user s manual table of contents table of contents chapter 1 hardware description ............................................................................................................................... . 1-2 features ............................................................................................................................... ..... 1-2 application ............................................................................................................................... . 1-2 pin configuration .................................................................................................................. 1-3 functional block .................................................................................................................. 1-5 pin description ........................................................................................................................ 1-6 part numbering ....................................................................................................................... 1-8 group expansion .................................................................................................................... 1-9 memory type ............................................................................................................................ 1-9 memory size ............................................................................................................................. 1- 9 packages ............................................................................................................................... .... 1-9 functional description .................................................................................................... 1-10 central processing unit (cpu) ............................................................................................ 1-10 memory ............................................................................................................................... ..... 1-14 i/o ports ............................................................................................................................... ... 1-16 interrupts ..................................................................................................................... ............ 1-23 key input interrupt (key-on wake up) ................................................................................ 1-27 timers ............................................................................................................................... ....... 1-28 serial i/o ............................................................................................................................... .. 1-30 pulse width modulation (pwm) output circuit .................................................................. 1-36 bus interface ........................................................................................................................... 1-39 multi-master i 2 c-bus interface ............................................................................................. 1-44 a-d converter ......................................................................................................................... 1-55 d-a converter ......................................................................................................................... 1-57 comparator circuit ................................................................................................................. 1-58 watchdog timer ..................................................................................................................... 1-59 reset circuit ........................................................................................................................... 1-60 clock generating circuit ....................................................................................................... 1-62 processor mode ...................................................................................................................... 1-65 bus control at memory expansion ...................................................................................... 1-66 eprom mode ......................................................................................................................... 1-67 flash memory mode .............................................................................................................. 1-68 notes on programming ..................................................................................................... 1-89 notes on usage ..................................................................................................................... 1-90 data required for mask orders ................................................................................ 1-90 data required for one time prom programming orders ............................. 1-90 functional description supplement ......................................................................... 1-91 chapter 2 application 2.1 i/o port ............................................................................................................................... ...... 2-2 2.1.1 memory map ................................................................................................................... 2-2 2.1.2 relevant registers .......................................................................................................... 2-3 2.1.3 port p4/p7 input register .............................................................................................. 2-5 2.1.4 handling of unused pins ............................................................................................... 2-5 2.1.5 notes on input and output pins ................................................................................... 2-6 2.1.6 termination of unused pins .......................................................................................... 2-7
3886 group user s manual table of contents 2.2 interrupt ............................................................................................................................... .... 2-8 2.2.1 memory map ................................................................................................................... 2-8 2.2.2 relevant registers .......................................................................................................... 2-8 2.2.3 interrupt source ............................................................................................................ 2-12 2.2.4 interrupt operation ........................................................................................................ 2-13 2.2.5 interrupt control ............................................................................................................ 2-16 2.2.6 int interrupt .................................................................................................................. 2-19 2.2.7 key input interrupt ....................................................................................................... 2-20 2.2.8 notes on interrupts ...................................................................................................... 2-22 2.3 timer ............................................................................................................................... ........ 2-24 2.3.1 memory map ................................................................................................................. 2-24 2.3.2 relevant registers ........................................................................................................ 2-24 2.3.3 timer application examples ........................................................................................ 2-30 2.3.4 notes on timer .............................................................................................................. 2-41 2.4 serial i/o ............................................................................................................................... . 2-42 2.4.1 memory map ................................................................................................................. 2-42 2.4.2 relevant registers ........................................................................................................ 2-43 2.4.3 serial i/o connection examples ................................................................................. 2-50 2.4.4 setting of serial i/o transfer data format ................................................................. 2-52 2.4.5 serial i/o application examples ................................................................................. 2-53 2.4.6 notes on serial i/o ...................................................................................................... 2-73 2.5 multi-master i 2 c-bus interface ......................................................................................... 2-76 2.5.1 memory map ................................................................................................................. 2-76 2.5.2 relevant registers ........................................................................................................ 2-76 2.5.3 i 2 c-bus overview ......................................................................................................... 2-83 2.5.4 communication format ................................................................................................. 2-84 2.5.5 synchronization and arbitration lost .......................................................................... 2-85 2.5.6 i 2 c-bus communication usage example ................................................................... 2-87 2.5.7 notes on multi-master i 2 c-bus interface ............................................................... 2-103 2.6 pwm ............................................................................................................................... ....... 2-106 2.6.1 memory map ............................................................................................................... 2-106 2.6.2 relevant registers ...................................................................................................... 2-107 2.6.3 pwm application example ......................................................................................... 2-111 2.6.4 notes on pwm ........................................................................................................... 2-113 2.7 a-d converter ..................................................................................................................... 2-114 2.7.1 memory map ............................................................................................................... 2-114 2.7.2 relevant registers ...................................................................................................... 2-114 2.7.3 a-d converter application examples ........................................................................ 2-118 2.7.4 notes on a-d converter ............................................................................................ 2-120 2.8 d-a converter ..................................................................................................................... 2-121 2.8.1 memory map ............................................................................................................... 2-121 2.8.2 relevant registers ...................................................................................................... 2-122 2.8.3 d-a converter application example .......................................................................... 2-124 2.8.4 notes on d-a converter ............................................................................................ 2-127 2.9 bus interface ...................................................................................................................... 2-128 2.9.1 memory map ............................................................................................................... 2-128 2.9.2 relevant registers ...................................................................................................... 2-129 2.9.3 bus interface overview .............................................................................................. 2-133 2.9.4 input/output operation ............................................................................................... 2-134 2.9.5 relevant registers setting ......................................................................................... 2-135 2.10 watchdog timer ................................................................................................................ 2-137 2.10.1 memory map ............................................................................................................. 2-137
3886 group user s manual table of contents 2.10.2 relevant registers .................................................................................................... 2-137 2.10.3 watchdog timer application examples ................................................................. 2-139 2.10.4 notes on watchdog timer ........................................................................................ 2-140 2.11 reset ............................................................................................................................... ...2-141 2.11.1 connection example of reset ic ............................................................................ 2-141 2.11.2 notes on reset pin ............................................................................................... 2-142 2.12 clock generating circuit ................................................................................................ 2-143 2.12.1 relevant registers .................................................................................................... 2-143 2.12.2 clock generating circuit application example ....................................................... 2-144 2.13 standby function ............................................................................................................. 2-147 2.13.1 stop mode ................................................................................................................. 2-147 2.13.2 wait mode ................................................................................................................. 2-151 2.14 processor mode ............................................................................................................... 2-154 2.14.1 memory map ............................................................................................................. 2-154 2.14.2 relevant registers .................................................................................................... 2-154 2.14.3 processor mode usage examples ........................................................................ 2-155 2.15 flash memory ................................................................................................................... 2-162 2.15.1 overview .................................................................................................................... 2-162 2.15.2 memory map ............................................................................................................. 2-162 2.15.3 relevant registers .................................................................................................... 2-163 2.15.4 parallel i/o mode ..................................................................................................... 2-164 2.15.5 serial i/o mode ........................................................................................................ 2-165 2.15.6 cpu reprogramming mode ..................................................................................... 2-166 2.15.7 flash memory mode application examples .......................................................... 2-167 2.15.8 notes on cpu reprogramming mode .................................................................... 2-176 chapter 3 appendix 3.1 electrical characteristics ..................................................................................................... 3-2 3.1.1 absolute maximum ratings ............................................................................................ 3-2 3.1.2 recommended operating conditions ............................................................................ 3-3 3.1.3 electrical characteristics ................................................................................................ 3-5 3.1.4 a-d converter characteristics ....................................................................................... 3-7 3.1.5 d-a converter characteristics ....................................................................................... 3-7 3.1.6 comparator characteristics ........................................................................................... 3-7 3.1.7 timing requirements ...................................................................................................... 3-8 3.1.8 timing requirements for system bus interface ......................................................... 3-10 3.1.9 switching characteristics ............................................................................................. 3-11 3.1.10 switching characteristics for system bus interface ............................................... 3-11 3.1.11 timing requirements in memory expansion mode and microprocessor mode .. 3-12 3.1.12 switching characteristics in memory expansion mode and microprocessor mode .. 3-12 3.1.13 multi-master i 2 c-bus bus line characteristics ....................................................... 3-17 3.2 standard characteristics .................................................................................................... 3-18 3.2.1 power source current characteristic examples ........................................................ 3-18 3.2.2 port standard characteristic examples ...................................................................... 3-22 3.2.3 input port standard characteristic examples ............................................................ 3-25 3.2.4 a-d conversion standard characteristics ................................................................... 3-26 3.2.5 d-a conversion standard characteristics ................................................................... 3-27 3.3 notes on use ........................................................................................................................ 3-28 3.3.1 notes on input and output pins ................................................................................. 3-28 3.3.2 termination of unused pins ........................................................................................ 3-29 3.3.3 notes on interrupts ...................................................................................................... 3-30 3.3.4 notes on timer .............................................................................................................. 3-31
3886 group user s manual table of contents 3.3.5 notes on serial i/o ...................................................................................................... 3-32 3.3.6 notes on multi-master i 2 c-bus interface ................................................................. 3-35 3.3.7 notes on pwm ............................................................................................................. 3-37 3.3.8 notes on a-d converter .............................................................................................. 3-37 3.3.9 notes on d-a converter .............................................................................................. 3-37 3.3.10 notes on watchdog timer .......................................................................................... 3-38 3.3.11 notes on reset pin ................................................................................................. 3-38 3.3.12 notes on cpu reprogramming mode ...................................................................... 3-38 3.3.13 notes on using stop mode ....................................................................................... 3-38 3.3.14 notes on wait mode .................................................................................................. 3-39 3.3.15 notes on low-speed operation mode ...................................................................... 3-39 3.3.16 notes on restarting oscillation .................................................................................. 3-39 3.3.17 notes on programming .............................................................................................. 3-40 3.3.18 programming and test of built-in prom version ................................................... 3-42 3.3.19 notes on built-in prom version .............................................................................. 3-43 3.4 countermeasures against noise ...................................................................................... 3-44 3.4.1 shortest wiring length .................................................................................................. 3-44 3.4.2 connection of bypass capacitor across vss line and vcc line ............................. 3-46 3.4.3 wiring to analog input pins ........................................................................................ 3-46 3.4.4 oscillator concerns ....................................................................................................... 3-47 3.4.5 setup for i/o ports ....................................................................................................... 3-48 3.4.6 providing of watchdog timer function by software .................................................. 3-49 3.5 list of registers ................................................................................................................... 3-50 3.6 package outline ................................................................................................................... 3-75 3.7 machine instructions .......................................................................................................... 3-76 3.8 list of instruction code ..................................................................................................... 3-87 3.9 sfr memory map ................................................................................................................ 3-88 3.10 pin configurations ........................................................................................................ ..... 3-89
3886 group user s manual list of figures list of figures chapter 1 hardware fig. 1 m3886 7m8a-xxxhp, m3886 7e8ahp pin configuration ................................................ 1-3 fig. 2 m3886 7e8afs pin configuration ...................................................................................... 1-3 fig. 3 m3886 9mfa-xxxgp/hp, m3886 9ffagp/hp pin configuration ................................... 1-4 fig. 4 functional block diagram ................................................................................................... 1-5 fig. 5 part numbering .................................................................................................................... 1-8 fig. 6 memory expansion plan ..................................................................................................... 1-9 fig. 7 740 family cpu register structure ................................................................................. 1-10 fig. 8 register push and pop at interrupt generation and subroutine call ......................... 1-11 fig. 9 structure of cpu mode register ..................................................................................... 1-13 fig. 10 memory map diagram .................................................................................................... 1-14 fig. 11 memory map of special function register (sfr) ........................................................ 1-15 fig. 12 port block diagram (1) ................................................................................................... 1-18 fig. 13 port block diagram (2) ................................................................................................... 1-19 fig. 14 port block diagram (3) ................................................................................................... 1-20 fig. 15 port block diagram (4) ................................................................................................... 1-21 fig. 16 structure of port i/o related registers ......................................................................... 1-22 fig. 17 interrupt control ............................................................................................................... 1-25 fig. 18 structure of interrupt-related registers (1) .................................................................. 1-25 fig. 19 structure of interrupt-related registers (2) .................................................................. 1-26 fig. 20 connection example when using key input interrupt and port p3 block diagram... 1-27 fig. 21 structure of timer xy mode register ............................................................................ 1-28 fig. 22 block diagram of timer x, timer y, timer 1, and timer 2 ......................................... 1-29 fig. 23 block diagram of clock synchronous serial i/o1 ........................................................ 1-30 fig. 24 operation of clock synchronous serial i/o1 function ................................................ 1-30 fig. 25 block diagram of uart serial i/o1 ............................................................................. 1-31 fig. 26 operation of uart serial i/o1 function ...................................................................... 1-32 fig. 27 structure of serial i/o1 control registers ..................................................................... 1-33 fig. 28 structure of serial i/o2 control register ....................................................................... 1-34 fig. 29 block diagram of serial i/o2 function .......................................................................... 1-34 fig. 30 timing of serial i/o2 function ....................................................................................... 1-35 fig. 31 pwm block diagram (pwm0) ........................................................................................ 1-36 fig. 32 pwm timing ..................................................................................................................... 1-37 fig. 33 14-bit pwm timing (pwm0) .......................................................................................... 1-38 fig. 34 interrupt request circuit of data bus buffer ................................................................. 1-39 fig. 35 structure of bus interface related register .................................................................. 1-40 fig. 36 bus interface device block diagram ............................................................................. 1-41 fig. 37 block diagram of multi-master i 2 c-bus interface ...................................................... 1-44 fig. 38 structure of i 2 c address register .................................................................................. 1-45 fig. 39 structure of i 2 c clock control register ......................................................................... 1-46 fig. 40 structure of i 2 c control register .................................................................................... 1-47 fig. 41 structure of i 2 c status register ..................................................................................... 1-49 fig. 42 interrupt request signal generating timing .................................................................. 1-49 fig. 43 start condition generating timing diagram .............................................................. 1-50 fig. 44 stop condition generating timing diagram ................................................................ 1-50 fig. 45 start condition detecting timing diagram ................................................................. 1-50
3886 group user s manual list of figures fig. 46 stop condition detecting timing diagram ................................................................... 1-50 fig. 47 structure of i 2 c start/stop condition control register ......................................... 1-52 fig. 48 address data communication format ............................................................................ 1-52 fig. 49 structure of ad/da control register ............................................................................. 1-55 fig. 50 structure of 10-bit a-d mode reading ......................................................................... 1-55 fig. 51 block diagram of a-d converter ................................................................................... 1-56 fig. 52 block diagram of d-a converter ................................................................................... 1-57 fig. 53 equivalent connection circuit of d-a converter (da1) ............................................... 1-57 fig. 54 comparator circuit .......................................................................................................... 1-58 fig. 55 block diagram of watchdog timer ................................................................................ 1-59 fig. 56 structure of watchdog timer control register ............................................................. 1-59 fig. 57 reset circuit example .................................................................................................... 1-60 fig. 58 reset sequence .............................................................................................................. 1-60 fig. 59 internal status at reset ............................................................................................... ... 1-61 fig. 60 ceramic resonator circuit .............................................................................................. 1-62 fig. 61 external clock input circuit ............................................................................................ 1-62 fig. 62 system clock generating circuit block diagram (single-chip mode) ........................ 1-63 fig. 63 state transitions of system clock ................................................................................. 1-64 fig. 64 memory maps in various processor modes ................................................................ 1-65 fig. 65 structure of cpu mode register ................................................................................... 1-65 fig. 66 onw function timing ...................................................................................................... 1-66 fig. 67 programming and testing of one time prom version ............................................ 1-67 fig. 68 pin connection of m3886 9ffahp/gp when operating in parallel input/output mode ... 1-70 fig. 69 read timing ..................................................................................................................... 1-71 fig. 70 timings during reading .................................................................................................. 1-72 fig. 71 input/output timings during programming (verify data is output at the same timing as for read.) ......................................................................................................................... 1-73 fig. 72 input/output timings during erasing (verify data is output at the same timing as for read.) ............................................................................................................................... 1-74 fig. 73 programming/erasing algorithm flow chart ................................................................. 1-76 fig. 74 pin connection of m3886 9ffahp/gp when operating in serial i/o mode ............ 1-78 fig. 75 timings during reading .................................................................................................. 1-80 fig. 76 timings during programming ......................................................................................... 1-81 fig. 77 timings during program verify ...................................................................................... 1-81 fig. 78 timings at erasing .......................................................................................................... 1-82 fig. 79 timings during erase verify ........................................................................................... 1-82 fig. 80 timings at error checking .............................................................................................. 1-83 fig. 81 flash memory control register bit configuration ......................................................... 1-85 fig. 82 flash command register bit configuration ................................................................... 1-86 fig. 83 cpu mode register bit configuration in cpu rewriting mode .................................. 1-86 fig. 84 flowchart of program/erase operation at cpu reprogramming mode .................... 1-88 fig. 85 a-d conversion equivalent circuit ................................................................................. 1-92 fig. 86 a-d conversion timing chart .......................................................................................... 1-92 chapter 2 application fig. 2.1.1 memory map of registers relevant to i/o port ......................................................... 2-2 fig. 2.1.2 structure of port pi (i = 0 to 8) ................................................................................. 2-3 fig. 2.1.3 structure of port pi direction register (i = 0 to 8) .................................................. 2-3 fig. 2.1.4 structure of port control register 1 ............................................................................ 2-4 fig. 2.1.5 structure of port control register 2 ............................................................................ 2-4 fig. 2.2.1 memory map of registers relevant to interrupt ........................................................ 2-8
3886 group user s manual list of figures fig. 2.2.2 structure of port control register 2 ............................................................................ 2-8 fig. 2.2.3 structure of interrupt source selection register ....................................................... 2-9 fig. 2.2.4 structure of interrupt edge selection register .......................................................... 2-9 fig. 2.2.5 structure of interrupt request register 1 ................................................................. 2-10 fig. 2.2.6 structure of interrupt request register 2 ................................................................. 2-10 fig. 2.2.7 structure of interrupt control register 1 .................................................................. 2-11 fig. 2.2.8 structure of interrupt control register 2 .................................................................. 2-11 fig. 2.2.9 interrupt operation diagram ....................................................................................... 2-13 fig. 2.2.10 changes of stack pointer and program counter upon acceptance of interrupt request .. 2-14 fig. 2.2.11 time up to execution of interrupt processing routine ......................................... 2-15 fig. 2.2.12 timing chart after acceptance of interrupt request ............................................. 2-15 fig. 2.2.13 interrupt control diagram ......................................................................................... 2-16 fig. 2.2.14 example of multiple interrupts ................................................................................ 2-18 fig. 2.2.15 connection example and port p3 block diagram when using key input interrupt .. 2-20 fig. 2.2.16 registers setting relevant to key input interrupt (corresponding to figure 2.2.15) ...2-21 fig. 2.2.17 sequence of switching detection edge ................................................................. 2-22 fig. 2.2.18 sequence of check of interrupt request bit .......................................................... 2-22 fig. 2.2.19 sequence of changing relevant register ............................................................... 2-23 fig. 2.3.1 memory map of registers relevant to timers .......................................................... 2-24 fig. 2.3.2 structure of prescaler 12, prescaler x, prescaler y ............................................ 2-24 fig. 2.3.3 structure of timer 1 .................................................................................................. 2-25 fig. 2.3.4 structure of timer 2, timer x, timer y ................................................................. 2-25 fig. 2.3.5 structure of timer xy mode register ...................................................................... 2-26 fig. 2.3.6 structure of port control register 2 .......................................................................... 2-27 fig. 2.3.7 structure of interrupt request register 1 ................................................................. 2-28 fig. 2.3.8 structure of interrupt request register 2 ................................................................. 2-28 fig. 2.3.9 structure of interrupt control register 1 .................................................................. 2-29 fig. 2.3.10 structure of interrupt control register 2 ................................................................ 2-29 fig. 2.3.11 timers connection and setting of division ratios ................................................. 2-31 fig. 2.3.12 relevant registers setting ....................................................................................... 2-31 fig. 2.3.13 control procedure ..................................................................................................... 2-32 fig. 2.3.14 peripheral circuit example ....................................................................................... 2-33 fig. 2.3.15 timers connection and setting of division ratios ................................................. 2-33 fig. 2.3.16 relevant registers setting ....................................................................................... 2-34 fig. 2.3.17 control procedure ..................................................................................................... 2-34 fig. 2.3.18 judgment method of valid/invalid of input pulses ............................................... 2-35 fig. 2.3.19 relevant registers setting ....................................................................................... 2-36 fig. 2.3.20 control procedure ..................................................................................................... 2-37 fig. 2.3.21 timers connection and setting of division ratios ................................................. 2-38 fig. 2.3.22 relevant registers setting ....................................................................................... 2-39 fig. 2.3.23 control procedure ..................................................................................................... 2-40 fig. 2.4.1 memory map of registers relevant to serial i/o .................................................... 2-42 fig. 2.4.2 structure of transmit/receive buffer register ........................................................ 2-43 fig. 2.4.3 structure of serial i/o status register ..................................................................... 2-43 fig. 2.4.4 structure of serial i/o1 control register .................................................................. 2-44 fig. 2.4.5 structure of uart control register .......................................................................... 2-44 fig. 2.4.6 structure of baud rate generator ............................................................................. 2-45 fig. 2.4.7 structure of serial i/o2 control register .................................................................. 2-45 fig. 2.4.8 structure of serial i/o2 register ............................................................................... 2-46 fig. 2.4.9 structure of interrupt source selection register ..................................................... 2-46 fig. 2.4.10 structure of interrupt edge selection register ...................................................... 2-47 fig. 2.4.11 structure of interrupt request register 1 ............................................................... 2-48
3886 group user s manual list of figures fig. 2.4.12 structure of interrupt request register 2 ............................................................... 2-48 fig. 2.4.13 structure of interrupt control register 1 ................................................................ 2-49 fig. 2.4.14 structure of interrupt control register 2 ................................................................ 2-49 fig. 2.4.15 serial i/o connection examples (1) ....................................................................... 2-50 fig. 2.4.16 serial i/o connection examples (2) ....................................................................... 2-51 fig. 2.4.17 serial i/o transfer data format ............................................................................... 2-52 fig. 2.4.18 connection diagram ................................................................................................. 2-53 fig. 2.4.19 timing chart .............................................................................................................. 2-53 fig. 2.4.20 registers setting relevant to transmitting side ..................................................... 2-54 fig. 2.4.21 registers setting relevant to receiving side ......................................................... 2-55 fig. 2.4.22 control procedure of transmitting side .................................................................. 2-56 fig. 2.4.23 control procedure of receiving side ...................................................................... 2-57 fig. 2.4.24 connection diagram ................................................................................................. 2-58 fig. 2.4.25 timing chart .............................................................................................................. 2-58 fig. 2.4.26 registers setting relevant to serial i/o1 .............................................................. 2-59 fig. 2.4.27 setting of serial i/o1 transmission data ............................................................... 2-59 fig. 2.4.28 control procedure of serial i/o1 ............................................................................ 2-60 fig. 2.4.29 registers setting relevant to serial i/o2 .............................................................. 2-61 fig. 2.4.30 setting of serial i/o2 transmission data ............................................................... 2-61 fig. 2.4.31 control procedure of serial i/o2 ............................................................................ 2-62 fig. 2.4.32 connection diagram ................................................................................................. 2-63 fig. 2.4.33 timing chart .............................................................................................................. 2-64 fig. 2.4.34 relevant registers setting ....................................................................................... 2-64 fig. 2.4.35 control procedure of master unit ........................................................................... 2-65 fig. 2.4.36 control procedure of slave unit ............................................................................. 2-66 fig. 2.4.37 connection diagram (communication using uart) ............................................ 2-67 fig. 2.4.38 timing chart (using uart) ..................................................................................... 2-67 fig. 2.4.39 registers setting relevant to transmitting side ..................................................... 2-69 fig. 2.4.40 registers setting relevant to receiving side ......................................................... 2-70 fig. 2.4.41 control procedure of transmitting side .................................................................. 2-71 fig. 2.4.42 control procedure of receiving side ...................................................................... 2-72 fig. 2.4.43 sequence of setting serial i/o1 control register again ....................................... 2-74 fig. 2.5.1 memory map of registers relevant to i 2 c-bus interface ...................................... 2-76 fig. 2.5.2 structure of i 2 c data shift register ........................................................................... 2-76 fig. 2.5.3 structure of i 2 c address register ............................................................................. 2-77 fig. 2.5.4 structure of i 2 c status register ................................................................................. 2-77 fig. 2.5.5 structure of i 2 c control register ............................................................................... 2-78 fig. 2.5.6 structure of i 2 c clock control register ..................................................................... 2-79 fig. 2.5.7 structure of i 2 c start/stop condition control register ..................................... 2-80 fig. 2.5.8 structure of interrupt source selection register ..................................................... 2-80 fig. 2.5.9 structure of interrupt request register 1 ................................................................. 2-81 fig. 2.5.10 structure of interrupt request register 2 ............................................................... 2-81 fig. 2.5.11 structure of interrupt control register 1 ................................................................ 2-82 fig. 2.5.12 structure of interrupt control register 2 ................................................................ 2-82 fig. 2.5.13 i 2 c-bus connection structure ................................................................................. 2-83 fig. 2.5.14 i 2 c-bus communication format example .............................................................. 2-84 fig. 2.5.15 restart condition of master reception .............................................................. 2-85 fig. 2.5.16 scl waveforms when synchronizing clocks ......................................................... 2-86 fig. 2.5.17 initial setting example .............................................................................................. 2-88 fig. 2.5.18 read word protocol communication as i 2 c-bus master device ....................... 2-89 fig. 2.5.19 generating of start condition and transmission process of slave address + write bit.. 2-90 fig. 2.5.20 transmission process of command ....................................................................... 2-91
3886 group user s manual list of figures fig. 2.5.21 transmission process of restart condition and slave address + read bit . 2-92 fig. 2.5.22 reception process of lower data ........................................................................... 2-93 fig. 2.5.23 reception process of upper data .......................................................................... 2-94 fig. 2.5.24 generating of stop condition ............................................................................... 2-95 fig. 2.5.25 communication example as slave device ............................................................. 2-96 fig. 2.5.26 reception process of start condition and slave address .............................. 2-97 fig. 2.5.27 reception process of command ............................................................................. 2-98 fig. 2.5.28 reception process of restart condition and slave address ......................... 2-99 fig. 2.5.29 transmission process of lower data .................................................................... 2-100 fig. 2.5.30 transmission process of upper data ................................................................... 2-101 fig. 2.5.31 reception of stop condition ............................................................................... 2-102 fig. 2.6.1 memory map of registers relevant to pwm ......................................................... 2-106 fig. 2.6.2 structure of port control register 1 ........................................................................ 2-107 fig. 2.6.3 structure of pwm0h register ................................................................................. 2-108 fig. 2.6.4 structure of pwm0l register .................................................................................. 2-108 fig. 2.6.5 structure of pwm1h register ................................................................................. 2-109 fig. 2.6.6 structure of pwm1l register .................................................................................. 2-109 fig. 2.6.7 structure of ad/da control register ....................................................................... 2-110 fig. 2.6.8 connection diagram ................................................................................................. 2-111 fig. 2.6.9 relevant registers setting ....................................................................................... 2-112 fig. 2.6.10 control procedure ................................................................................................... 2-113 fig. 2.6.11 pwm 0 output ........................................................................................................... 2-113 fig. 2.7.1 memory map of registers relevant to a-d converter .......................................... 2-114 fig. 2.7.2 structure of ad/da control register ....................................................................... 2-114 fig. 2.7.3 structure of a-d conversion register 1 ................................................................. 2-115 fig. 2.7.4 structure of a-d conversion register 2 ................................................................. 2-115 fig. 2.7.5 structure of interrupt source selection register ................................................... 2-116 fig. 2.7.6 structure of interrupt request register 2 ............................................................... 2-117 fig. 2.7.7 structure of interrupt control register 2 ................................................................ 2-117 fig. 2.7.8 connection diagram ................................................................................................. 2-118 fig. 2.7.9 relevant registers setting ....................................................................................... 2-118 fig. 2.7.10 control procedure for 8-bit read .......................................................................... 2-119 fig. 2.7.11 control procedure for 10-bit read ........................................................................ 2-119 fig. 2.8.1 memory map of registers relevant to d-a converter .......................................... 2-121 fig. 2.8.2 structure of port p5 direction register .................................................................. 2-122 fig. 2.8.3 structure of ad/da control register ....................................................................... 2-122 fig. 2.8.4 structure of d-ai converter register ...................................................................... 2-123 fig. 2.8.5 peripheral circuit example ....................................................................................... 2-124 fig. 2.8.6 speaker output example ......................................................................................... 2-124 fig. 2.8.7 relevant registers setting ....................................................................................... 2-125 fig. 2.8.8 control procedure ..................................................................................................... 2-126 fig. 2.9.1 memory map of registers relevant to bus interface ............................................ 2-128 fig. 2.9.2 structure of data bus buffer register i .................................................................. 2-129 fig. 2.9.3 structure of data bus buffer status register i ...................................................... 2-129 fig. 2.9.4 structure of data bus buffer control register ....................................................... 2-130 fig. 2.9.5 structure of interrupt source selection register ................................................... 2-130 fig. 2.9.6 structure of interrupt request register 1 ............................................................... 2-131 fig. 2.9.7 structure of interrupt control register 1 ................................................................ 2-131 fig. 2.9.8 structure of port control register 2 ........................................................................ 2-132 fig. 2.9.9 bus interface block diagram ................................................................................... 2-133 fig. 2.9.10 relevant registers setting ..................................................................................... 2-135 fig. 2.9.11 control procedure using interrupt ........................................................................ 2-136
3886 group user s manual list of figures fig. 2.10.1 memory map of registers relevant to watchdog timer ...................................... 2-137 fig. 2.10.2 structure of watchdog timer control register ..................................................... 2-137 fig. 2.10.3 structure of cpu mode register .......................................................................... 2-138 fig. 2.10.4 watchdog timer connection and division ratio setting ...................................... 2-139 fig. 2.10.5 relevant registers setting ..................................................................................... 2-140 fig. 2.10.6 control procedure ................................................................................................... 2-140 fig. 2.11.1 example of poweron reset circuit ........................................................................ 2-141 fig. 2.11.2 ram backup system .............................................................................................. 2-141 fig. 2.12.1 structure of cpu mode register .......................................................................... 2-143 fig. 2.12.2 connection diagram ............................................................................................... 2-144 fig. 2.12.3 status transition diagram during power failure .................................................. 2-144 fig. 2.12.4 setting of relevant registers ................................................................................. 2-145 fig. 2.12.5 control procedure ................................................................................................... 2-146 fig. 2.13.1 oscillation stabilizing time at restoration by reset input .................................. 2-148 fig. 2.13.2 execution sequence example at restoration by occurrence of int 0 interrupt request .. 2-150 fig. 2.13.3 reset input time ..................................................................................................... 2-152 fig. 2.14.1 memory map of registers relevant to processor mode ..................................... 2-154 fig. 2.14.2 structure of cpu mode register .......................................................................... 2-154 fig. 2.14.3 expansion example of 32-kbytes rom and ram ............................................ 2-155 fig. 2.14.4 read cycle (oe access, sram) .......................................................................... 2-156 fig. 2.14.5 read cycle (oe access, eprom) ....................................................................... 2-156 fig. 2.14.6 write cycle (w control, sram) ............................................................................ 2-157 fig. 2.14.7 usage example of onw function ........................................................................ 2-158 fig. 2.14.8 expansion example of 32-kbytes rom and ram at f(x in ) = 8 mhz or more ... 2-159 fig. 2.14.9 read cycle (oe access, sram) .......................................................................... 2-160 fig. 2.14.10 read cycle (oe access, eprom) ..................................................................... 2-160 fig. 2.14.11 write cycle (w control, sram) .......................................................................... 2-161 fig. 2.15.1 memory map of flash memory version for 3886 group ................................... 2-162 fig. 2.15.2 memory map of registers relevant to flash memory ......................................... 2-163 fig. 2.15.3 structure of flash memory control register ........................................................ 2-163 fig. 2.15.4 structure of flash command register .................................................................. 2-164 fig. 2.15.5 reprogramming example of built-in flash memory in serial i/o mode ........... 2-167 fig. 2.15.6 connection example in serial i/o mode (1) ....................................................... 2-168 fig. 2.15.7 connection example in serial i/o mode (2) ....................................................... 2-168 fig. 2.15.8 connection example in serial i/o mode (3) ....................................................... 2-169 fig. 2.15.9 example of reprogramming system for built-in flash memory in cpu reprogramming mode ... 2-170 fig. 2.15.10 cpu reprogramming control program example (1) ......................................... 2-171 fig. 2.15.11 cpu reprogramming control program example (2) ......................................... 2-172 fig. 2.15.12 cpu reprogramming control program example (3) ......................................... 2-173 fig. 2.15.13 cpu reprogramming control program example (4) ......................................... 2-174 fig. 2.15.14 v pp control circuit example (1) ........................................................................... 2-175 fig. 2.15.15 v pp control circuit example (2) ........................................................................... 2-175 chapter 3 appendix fig. 3.1.1 circuit for measuring output switching characteristics (1) ................................... 3-12 fig. 3.1.2 circuit for measuring output switching characteristics (2) ................................... 3-12 fig. 3.1.3 timing diagram (1) (in single-chip mode) ............................................................... 3-13 fig. 3.1.4 timing diagram (2) (in memory expansion mode and microprocessor mode) .. 3-14 fig. 3.1.5 timing diagram (3) (in memory expansion mode and microprocessor mode) .. 3-15 fig. 3.1.6 timing diagram (4) (system bus interface) ............................................................ 3-16
3886 group user s manual list of figures fig. 3.1.7 timing diagram of multi-master i 2 c-bus ................................................................ 3-17 fig. 3.2.1 power source current characteristic examples (in high-speed mode, a-d conversion and comparator operating) ........................................................................................ 3-18 fig. 3.2.2 power source current characteristic examples (in high-speed mode) ................ 3-18 fig. 3.2.3 power source current characteristic examples (in high-speed mode, wait execution) . 3-19 fig. 3.2.4 power source current characteristic examples (in middle-speed mode) ............ 3-19 fig. 3.2.5 power source current characteristic examples (in middle-speed mode, wait execution) . 3-20 fig. 3.2.6 power source current characteristic examples (in low-speed mode) ................. 3-20 fig. 3.2.7 power source current characteristic examples (at reset) ..................................... 3-21 fig. 3.2.8 standard characteristic examples of cmos output port at p-channel drive (ta=25 c) .. 3-22 fig. 3.2.9 standard characteristic examples of cmos output port at p-channel drive (ta=90 c) ... 3-22 fig. 3.2.10 standard characteristic examples of cmos output port at n-channel drive (ta=25 c) ... 3-23 fig. 3.2.11 standard characteristic examples of cmos output port at n-channel drive (ta=90 c) .. 3-23 fig. 3.2.12 standard characteristic examples of cmos large current output port at n-channel drive (ta=25 c) ...................................................................................................... 3-24 fig. 3.2.13 standard characteristic examples of cmos large current output port at n-channel drive (ta=90 c) ...................................................................................................... 3-24 fig. 3.2.14 standard characteristic examples of cmos input port at pull-up (ta=25 c) .. 3-25 fig. 3.2.15 standard characteristic examples of cmos input port at pull-up (ta=90 c) .. 3-25 fig. 3.2.16 a-d conversion standard characteristics ............................................................... 3-26 fig. 3.2.17 d-a conversion standard characteristics ............................................................... 3-27 fig. 3.3.1 sequence of switch the detection edge .................................................................. 3-30 fig. 3.3.2 sequence of check of interrupt request bit ............................................................ 3-30 fig. 3.3.3 sequence of changing relevant register ................................................................. 3-31 fig. 3.3.4 sequence of setting serial i/o1 control register again ......................................... 3-33 fig. 3.3.5 pwm 0 output ............................................................................................................... 3-37 fig. 3.3.6 ceramic resonator circuit .......................................................................................... 3-39 fig. 3.3.7 initialization of processor status register ................................................................ 3-40 fig. 3.3.8 sequence of plp instruction execution .................................................................. 3-40 fig. 3.3.9 stack memory contents after php instruction execution ..................................... 3-40 fig. 3.3.10 interrupt routine .................................................................................................. ...... 3-41 fig. 3.3.11 status flag at decimal calculations ........................................................................ 3-41 fig. 3.3.12 programming and testing of one time prom version ...................................... 3-42 fig. 3.4.1 wiring for the reset pin ......................................................................................... 3-44 fig. 3.4.2 wiring for clock i/o pins ........................................................................................... 3-44 fig. 3.4.3 wiring for cnvss pin ................................................................................................. 3-45 fig. 3.4.4 wiring for the v pp pin of the one time prom version and the eprom version ... 3-45 fig. 3.4.5 bypass capacitor across the vss line and the vcc line ....................................... 3-46 fig. 3.4.6 analog signal line and a resistor and a capacitor ................................................ 3-46 fig. 3.4.7 wiring for a large current signal line ...................................................................... 3-47 fig. 3.4.8 wiring of reset pin ................................................................................................. 3-47 fig. 3.4.9 vss pattern on the underside of an oscillator ....................................................... 3-48 fig. 3.4.10 setup for i/o ports ................................................................................................... 3-48 fig. 3.4.11 watchdog timer by software ................................................................................... 3-49 fig. 3.5.1 structure of port pi .................................................................................................... 3-50 fig. 3.5.2 structure of port pi direction register ..................................................................... 3-50 fig. 3.5.3 structure of i 2 c data shift register ........................................................................... 3-51 fig. 3.5.4 structure of i 2 c address register ............................................................................. 3-51 fig. 3.5.5 structure of i 2 c status register ................................................................................. 3-52 fig. 3.5.6 structure of i 2 c control register ............................................................................... 3-53 fig. 3.5.7 structure of i 2 c clock control register ..................................................................... 3-54 fig. 3.5.8 structure of i 2 c start/stop condition control register ..................................... 3-55
3886 group user s manual list of figures fig. 3.5.9 structure of transmit/receive buffer register ........................................................ 3-55 fig. 3.5.10 structure of serial i/o1 status register ................................................................. 3-56 fig. 3.5.11 structure of serial i/o1 control register ................................................................ 3-56 fig. 3.5.12 structure of uart control register ........................................................................ 3-57 fig. 3.5.13 structure of baud rate generator ........................................................................... 3-57 fig. 3.5.14 structure of serial i/o2 control register ................................................................ 3-58 fig. 3.5.15 structure of watchdog timer control register ....................................................... 3-58 fig. 3.5.16 structure of serial i/o2 register ............................................................................. 3-59 fig. 3.5.17 structure of prescaler 12, prescaler x, prescaler y .......................................... 3-59 fig. 3.5.18 structure of timer 1 ................................................................................................ 3-60 fig. 3.5.19 structure of timer 2, timer x, timer y ............................................................... 3-60 fig. 3.5.20 structure of timer xy mode register .................................................................... 3-61 fig. 3.5.21 structure of data bus buffer register .................................................................... 3-62 fig. 3.5.22 structure of data bus buffer status register ........................................................ 3-62 fig. 3.5.23 structure of data bus buffer control register ....................................................... 3-63 fig. 3.5.24 structure of comparator data register .................................................................. 3-63 fig. 3.5.25 structure of port control register 1 ....................................................................... 3-64 fig. 3.5.26 structure of port control register 2 ....................................................................... 3-64 fig. 3.5.27 structure of pwm0h register ................................................................................. 3-65 fig. 3.5.28 structure of pwm0l register .................................................................................. 3-65 fig. 3.5.29 structure of pwm1h register ................................................................................. 3-66 fig. 3.5.30 structure of pwm1l register .................................................................................. 3-66 fig. 3.5.31 structure of ad/da control register ....................................................................... 3-67 fig. 3.5.32 structure of ad conversion register 1 .................................................................. 3-67 fig. 3.5.33 structure of d-ai conversion register .................................................................... 3-68 fig. 3.5.34 structure of a-d conversion register 2 ................................................................. 3-68 fig. 3.5.35 structure of interrupt source selection register ................................................... 3-69 fig. 3.5.36 structure of interrupt edge selection register ...................................................... 3-69 fig. 3.5.37 structure of cpu mode register ............................................................................ 3-70 fig. 3.5.38 structure of interrupt request register 1 ............................................................... 3-71 fig. 3.5.39 structure of interrupt request register 2 ............................................................... 3-71 fig. 3.5.40 structure of interrupt control register 1 ................................................................ 3-72 fig. 3.5.41 structure of interrupt control register 2 ................................................................ 3-72 fig. 3.5.42 structure of flash memory control register .......................................................... 3-73 fig. 3.5.43 structure of flash command register .................................................................... 3-74 fig. 3.10.1 m3886 7m8a-xxxhp, m3886 7e8ahp pin configuration ..................................... 3-89 fig. 3.10.2 m3886 7e8afs pin configuration ............................................................................ 3-89 fig. 3.10.3 m3886 9mfa-xxxgp/hp, m3886 9ffagp/hp pin configuration ........................ 3-90
3886 group user s manual list of tables list of tables chapter 1 hardware table 1 pin description (1) ........................................................................................................... 1-6 table 2 pin description (2) ........................................................................................................... 1-7 table 3 support products ............................................................................................................. 1-9 table 4 push and pop instructions of accumulator or processor status register ............... 1-11 table 5 set and clear instructions of each bit of processor status register ....................... 1-12 table 6 i/o port function (1) ...................................................................................................... 1-16 table 7 i/o port function (2) ...................................................................................................... 1-17 table 8 interrupt vector addresses and priority ...................................................................... 1-24 table 9 relationship between low-order 6 bits of data and period set by the add bit ... 1-37 table 10 function description of control i/o pins at bus interface function selected ....... 1-43 table 11 multi-master i 2 c-bus interface functions ................................................................. 1-44 table 12 set values of i 2 c clock control register and s cl frequency .................................. 1-46 table 13 start condition generating timing table ................................................................ 1-50 table 14 stop condition generating timing table .................................................................. 1-50 table 15 start condition/stop condition detecting conditions .......................................... 1-50 table 16 recommended set value to start/stop condition set bits (ssc4-ssc0) for each oscillation frequency ................................................................................................... 1-52 table 17 port functions in memory expansion mode and microprocessor mode ............... 1-65 table 18 programming adapter .................................................................................................. 1-67 table 19 prom programmer setup ........................................................................................... 1-67 table 20 pin assignments of m3886 9ffahp/gp when operating in the parallel input/output mode ............................................................................................................................. 1- 68 table 21 assignment states of control input and each state ................................................ 1-68 table 22 pin description (flash memory parallel i/o mode) .................................................. 1-69 table 23 software command (parallel input/output mode) .................................................... 1-71 table 24 dc electrical characteristics ....................................................................................... 1-77 table 25 read-only mode ........................................................................................................... 1-77 table 26 read/write mode ......................................................................................................... 1-77 table 27 pin description (flash memory serial i/o mode) ..................................................... 1-79 table 28 software command (serial i/o mode) ....................................................................... 1-80 table 29 ac electrical characteristics ....................................................................................... 1-84 table 30 relative formula for a reference voltage v ref of a-d converter and v ref ..................... 1-91 table 31 change of a-d conversion register during a-d conversion .................................. 1-91 chapter 2 application table 2.1.1 handling of unused pins (in single-chip mode) .................................................... 2-5 table 2.1.2 handling of unused pins (in memory expansion mode, microprocessor mode) ...2-5 table 2.2.1 interrupt sources, vector addresses and priority of 3886 group ...................... 2-12 table 2.2.2 list of interrupt bits according to interrupt source ............................................. 2-17 table 2.3.1 cntr 0 /cntr 1 active edge selection bit function ............................................... 2-26 table 2.4.1 setting examples of baud rate generator values and transfer bit rate values ... 2-68 table 2.5.1 set value of i 2 c clock control register and scl frequency .............................. 2-79 table 2.9.1 bus control signals and data bus status ........................................................... 2-134 table 2.13.1 state in stop mode ............................................................................................. 2-147 table 2.13.2 state in wait mode .............................................................................................. 2-151 table 2.15.1 setting of eprom programmers when parallel programming ...................... 2-164
3886 group user s manual list of tables table 2.15.2 connection example to programmer when serial programming ................... 2-165 chapter 3 appendix table 3.1.1 absolute maximum ratings ....................................................................................... 3-2 table 3.1.2 recommended operating conditions (1) ................................................................ 3-3 table 3.1.3 recommended operating conditions (2) ................................................................ 3-4 table 3.1.4 recommended operating conditions (3) ................................................................ 3-4 table 3.1.5 electrical characteristics (1) ..................................................................................... 3-5 table 3.1.6 electrical characteristics (2) ..................................................................................... 3-6 table 3.1.7 a-d converter characteristics (1) ............................................................................ 3-7 table 3.1.8 a-d converter characteristics (2) ............................................................................ 3-7 table 3.1.9 d-a converter characteristics .................................................................................. 3-7 table 3.1.10 comparator characteristics .................................................................................... 3-7 table 3.1.11 timing requirements (1) ......................................................................................... 3-8 table 3.1.12 timing requirements (2) ......................................................................................... 3-9 table 3.1.13 timing requirements for system bus interface (1) ........................................... 3-10 table 3.1.14 timing requirements for system bus interface (2) ........................................... 3-10 table 3.1.15 switching characteristics (1) ................................................................................ 3-11 table 3.1.16 switching characteristics (2) ................................................................................ 3-11 table 3.1.17 switching characteristics for system bus interface (1) .................................... 3-11 table 3.1.18 switching characteristics for system bus interface (2) .................................... 3-11 table 3.1.19 timing requirements in memory expansion mode and microprocessor mode . 3-12 table 3.1.20 switching characteristics in memory expansion mode and microprocessor mode .. 3-12 table 3.1.21 multi-master i 2 c-bus bus line characteristics .................................................. 3-17 table 3.3.1 programming adapters ........................................................................................... 3-43 table 3.3.2 prom programmer address setting ..................................................................... 3-43 table 3.5.1 set value of i 2 c clock control register and scl frequency .............................. 3-54 table 3.5.2 cntr 0 /cntr 1 active edge selection bit function ............................................... 3-61
3886 group user? manual description the 3886 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 3886 group is designed for controlling systems that require analog signal processing and include two serial i/o functions, a-d converters, d-a converters, system data bus interface function, watchdog timer, and comparator circuit. the multi-master i 2 c-bus interface can be added by option. features basic machine-language instructions ...................................... 71 minimum instruction execution time .................................. 0.4 s (at 10 mhz oscillation frequency) memory size rom ................................................................. 32k to 60k bytes ram ............................................................... 1024 to 2048 bytes programmable input/output ports ............................................ 72 software pull-up resistors ................................................. built-in interrupts ................................................. 21 sources, 16 vectors (included key input interrupt) timers ............................................................................. 8-bit ? 4 serial i/o1 .................... 8-bit ? 1(uart or clock-synchronized) serial i/o2 ................................... 8-bit ? 1(clock-synchronized) pwm output circuit ....................................................... 14-bit ? 2 bus interface .................................................................... 2 bytes i 2 c-bus interface (option) ........................................... 1 channel a-d converter ............................................... 10-bit ? 8 channels d-a converter ................................................. 8-bit ? 2 channels comparator circuit ...................................................... 8 channels watchdog timer ............................................................ 16-bit ? 1 clock generating circuit ..................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage in high-speed mode .................................................. 4.0 to 5.5 v (at 10 mhz oscillation frequency) in middle-speed mode ........................................... 2.7 to 5.5 v(*) (at 10 mhz oscillation frequency) in low-speed mode ............................................... 2.7 to 5.5 v (*) (at 32 khz oscillation frequency) (*: 4.0 to 5.5 v for flash memory version) power dissipation in high-speed mode .......................................................... 40 mw (at 10 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................................ 60 w (at 32 khz oscillation frequency, at 3 v power source voltage) memory expansion possible (only for m3886 7m8a/e8a) operating temperature range .................................... ?0 to 85? supply voltage (at programming/erasing) ...... v cc = 5 v ?10 % program/erase voltage ............................... v pp = 11.7 to 12.6 v programming method ...................... programming in unit of byte erasing method batch erasing ........................................ parallel/serial i/o mode block erasing .................................... cpu reprogramming mode program/erase control by software command number of times for programming/erasing ............................ 100 operating temperature range (at programming/erasing) ..................................................................... normal temperature notes 1. the flash memory version cannot be used for application em- bedded in the mcu card. 2. power source voltage vcc of the flash memory version is 4.0 to 5.5 v. application household product, consumer electronics, communications, note book pc, etc. description/features
3886 group user? manual hardware package type : 80d0 pin configuration (top view) note: the pin number and the position of the function pin may change by the kind of package. fig. 2 m3886 7e8afs pin configuration package type : 80p6q-a pin configuration (top view) note: the pin number and the position of the function pin may change by the kind of package. fig. 1 m3886 7m8a-xxxhp, m3886 7e8ahp pin configuration : prom version pin configuration : prom version 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p 3 0 / p w m 0 0 p 3 1 / p w m 1 0 p 6 2 / a n 2 p 6 1 / a n 1 p 4 4 / r x d p 4 3 / i n t 1 / o b f 0 1 p 6 3 / a n 3 p 6 4 / a n 4 p 6 5 / a n 5 p 6 6 / a n 6 a v s s p 6 7 / a n 7 v r e f v c c p 8 0 / d q 0 p 8 1 / d q 1 p 8 2 / d q 2 p 8 3 / d q 3 p 8 4 / d q 4 p 8 5 / d q 5 p 8 6 / d q 6 p8 7 /dq 7 p 4 2 / i n t 0 / o b f 0 0 c n v s s x in x out v ss r e s e t p4 0 /x cou t p4 1 /x cin p1 6 /ad 14 p1 7 /ad 15 p2 6 /db 6 p2 5 /db 5 p2 4 /db 4 p2 3 /db 3 p2 2 /db 2 p2 1 /db 1 p 2 0 / d b 0 p 3 4 /
3886 group user s manual fig. 3 m3886 9mfa-xxxgp/hp, m3886 9ffagp/hp pin configuration note: the pin number and the position of the function pin may change by the kind of package. : flash memory version package type : 80p6s-a/80p6q-a pin configuration (top view) pin configuration 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 p 3 0 / p w m 0 0 p 3 1 / p w m 1 0 p 6 2 / a n 2 p 6 1 / a n 1 p 4 4 / r x d p 4 3 / i n t 1 / o b f 0 1 p 6 3 / a n 3 p 6 4 / a n 4 p 6 5 / a n 5 p 6 6 / a n 6 a v s s p 6 7 / a n 7 v r e f v c c p 8 0 / d q 0 p 8 1 / d q 1 p 8 2 / d q 2 p 8 3 / d q 3 p 8 4 / d q 4 p 8 5 / d q 5 p 8 6 / d q 6 p 8 7 / d q 7 p 4 2 / i n t 0 / o b f 0 0 c n v s s x i n x o u t v s s r e s e t p 4 0 / x c o u t p 4 1 / x c i n p 1 6 p 1 7 p 2 6 p 2 5 p 2 4 p 2 3 p 2 2 p 2 1 p 2 0 p 3 4 p 3 5 p 0 0 / p 3 r e f p 0 4 p 0 5 p 0 6 p 0 7 p 1 1 p 1 2 p 1 3 p 1 4 p 1 5 p 1 0 p 0 1 p 0 2 p 3 2 p 3 3 p 3 6 p 3 7 p 0 3 p 2 7 p 6 0 / a n 0 p 7 7 / s c l p 7 6 / s d a p 7 5 / i n t 4 1 p 7 4 / i n t 3 1 p 7 2 / s c l k 2 p 7 1 / s o u t 2 p 7 0 / s i n 2 p 5 7 / d a 2 / p w m 1 1 p 5 0 / a 0 p 4 5 / t x d p 7 3 / s r d y 2 / i n t 2 1 p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 6 / d a 1 / p w m 0 1 p 4 7 / s r d y 1 / s 1 p 5 2 / i n t 3 0 / r p 5 3 / i n t 4 0 / w p 5 1 / i n t 2 0 / s 0 p 4 6 / s c l k 1 / o b f 1 0 1 2 3 4 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 6 m 3 8 8 6 9 m f a - x x x g p / h p m 3 8 8 6 9 f f a g p / h p v p p
3886 group user s manual hardware functional block diagram (package : 80p6q-a, 80p6s-a) fig. 4 functional block diagram functional block i n t 0 , c n t r 0 c n t r 1 v r e f a v s s r a m r o m c p u a x y s p c h p c l p s v s s 3 0 r e s e t 2 5 v c c 7 1 2 4 c n v s s p 5 ( 8 ) p 7 ( 8 ) 2 4 6 8 3 5 7 9 p 8 ( 8 ) p 6 ( 8 ) 7 4 7 6 7 8 8 0 7 5 7 7 7 9 1 7 2 7 3 x i n 2 8 2 9 s i / o 1 ( 8 ) s i / o 2 ( 8 ) d - a c o n v e r t e r 2 ( 8 ) r e s e t i n p u t c l o c k g e n e r a t i n g c i r c u i t m a i n - c l o c k i n p u t m a i n - c l o c k o u t p u t a - d c o n v e r t e r ( 1 0 ) t i m e r y ( 8 ) t i m e r x ( 8 ) p r e s c a l e r 1 2 ( 8 ) p r e s c a l e r x ( 8 ) p r e s c a l e r y ( 8 ) t i m e r 1 ( 8 ) t i m e r 2 ( 8 ) i / o p o r t p 5 i / o p o r t p 7 i / o p o r t p 8 i / o p o r t p 6 s u b - c l o c k i n p u t x o u t x c i n x c o u t s u b - c l o c k o u t p u t w a t c h d o g t i m e r r e s e t p 0 ( 8 ) p 1 ( 8 ) p 2 ( 8 ) p 3 ( 8 ) i / o p o r t p 0 i / o p o r t p 1 i / o p o r t p 2 i / o p o r t p 3 p 3 r e f k e y - o n w a k e - u p x c i n x c o u t p 4 ( 8 ) i / o p o r t p 4 c o m p a r a t o r i n t 1 p w m 0 ( 1 4 ) p w m 1 ( 1 4 ) p w m 0 0 , p w m 0 1 p w m 1 0 , p w m 1 1 d q 0 t o d q 7 b u s i n t e r f a c e i c 2 s c l s d a i n t 4 1 i n t 2 1 , i n t 3 1 , i n t 4 0 i n t 2 0 , i n t 3 0 , 6 3 6 5 6 7 6 9 6 4 6 6 6 8 7 0 d - a c o n v e r t e r 1 ( 8 ) 1 0 1 2 1 4 1 6 1 1 1 3 1 5 1 7 1 8 2 0 2 2 2 6 1 9 2 1 2 3 2 7 5 5 5 7 5 9 6 1 5 6 5 8 6 0 6 2 3 1 3 3 3 5 3 7 3 2 3 4 3 6 3 8 3 9 4 1 4 3 4 5 4 0 4 2 4 4 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 functional block
3886 group user s manual v cc , v ss pin description functions name pin apply voltage of 2.7 v 5.5 v to vcc, and 0 v to vss. in the flash memory version, apply voltage of 4.0 v 5.5 v to vcc, and 0 v to vss. this pin controls the operation mode of the chip. normally connected to v ss . if this pin is connected to vcc, the internal rom is inhibited and an external memory is accessed. in the flash memory version, connected to v ss. in the eprom version or the flash memory version, this pin functions as the v pp power source input pin. reference voltage input pin for a-d and d-a converters. analog power source input pin for a-d and d-a converters. connect to v ss . reset input pin for active l . input and output pins for the clock generating circuit. connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. when the external memory is used, these pins are used as the address bus. cmos compatible input level. cmos 3-state output structure or n-channel open-drain output structure. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. when the external memory is used, these pins are used as the address bus. cmos compatible input level. cmos 3-state output structure or n-channel open-drain output structure. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. when the external memory is used, these pins are used as the data bus. cmos compatible input level. cmos 3-state output structure. p2 4 to p2 7 (4 bits) are enabled to output large current for led drive (only in single-chip mode). 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. when the external memory is used, these pins are used as the control bus. cmos compatible input level. cmos 3-state output structure. these pins function as key-on wake-up and compara- tor input. these pins are enabled to control pull-up. power source table 1 pin description (1) function except a port function comparator reference power source input pin key-on wake-up input pin comparator input pin pwm output pin key-on wake-up input pin comparator input pin reference voltage analog power source clock input clock output i/o port p0 i/o port p1 i/o port p2 v ref av ss p3 0 /pwm 00 p3 1 /pwm 10 cnv ss input cnv ss reset reset input x in x out p0 0 /p3 ref p0 1 p0 7 p1 0 p1 7 p2 0 p2 7 i/o port p3 p3 2 p3 7 pin description
3886 group user s manual hardware p5 1 /int 20 /s 0 p5 2 /int 30 /r p5 3 /int 40 /w functions name pin p4 0 /x cout p4 1 /x cin i/o port p4 8-bit i/o port with the same function as port p0. p4 0 , p4 1 , p4 7 : cmos 3-state output structure p4 2 p4 6 : cmos 3-state output structure or n- channel open-drain output structure regardless of input or output port, p4 2 to p4 6 can be input every pin level. when p4 2 and p4 3 are used as output port, the function which makes p4 2 and p4 3 clear to 0 when the host cpu reads the output data bus buffer 0 can be added. 8-bit i/o port with the same function as port p0. cmos compatible input level. cmos 3-state output structure. p5 0 to p5 3 can be switched between cmos com- patible input level or ttl input level in the bus interface function. function except a port function table 2 pin description (2) sub-clock generating circuit i/o pins (connect a resonator.) p4 2 /int 0 /obf 00 p4 3 /int 1 /obf 01 p4 4 /rxd p4 5 /txd p4 6 /s clk1 /obf 10 p4 7 /s rdy1 /s 1 p5 0 /a 0 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /da 1 /pwm 01 p5 7 /da 2 /pwm 11 p6 0 /an 0 p6 7 /an 7 p7 0 /s in2 p7 1 /s out2 p7 2 /s clk2 p7 3 /s rdy2 /int 21 p7 4 /int 31 p7 5 /int 41 p7 6 /s da p7 7 /s cl p8 0 /dq 0 p8 7 /dq 7 i/o port p5 i/o port p6 i/o port p7 i/o port p8 8-bit i/o port with the same function as port p0. cmos compatible input level. cmos 3-state output structure. 8-bit i/o port with the same function as port p0. p7 0 p7 5 : cmos compatible input level or ttl in- put level p7 6 , p7 7 : cmos compatible input level or smbus input level in the i 2 c-bus inter- face function, n-channel open-drain output structure regardless of input or output port, p7 0 to p7 5 can be input every pin level. 8-bit i/o port with the same function as port p0. cmos compatible input level. cmos 3-state output structure. cmos compatible input level or ttl input level in the bus interface function. interrupt input pins bus interface function pins serial i/o1 function pins serial i/o1 function pins bus interface function pins bus interface function pins interrupt input pins bus interface function pins timer x, timer y function pins d-a converter output pin pwm output pin a-d converter output pin serial i/o2 function pin serial i/o2 function pin interrupt input pin interrupt input pin i 2 c-bus interface function pin bus interface function pin pin description
3886 group user s manual part numbering fig. 5 part numbering part numbering m3886 7 m 8 a- xxx hp p r o d u c t n a m e package type hp : 80p6q-a gp : 80p6s-a fs : 80d0 rom number omitted in the one time prom version shipped in blank, the eprom version and the flash memory version. r o m / p r o m s i z e 1 2 3 4 5 6 7 8 : 4 0 9 6 b y t e s : 8 1 9 2 b y t e s : 1 2 2 8 8 b y t e s : 1 6 3 8 4 b y t e s : 2 0 4 8 0 b y t e s : 2 4 5 7 6 b y t e s : 2 8 6 7 2 b y t e s : 3 2 7 6 8 b y t e s the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. however, they can be programmed or erased in the eprom version and the flash memory version, so that the users can use them. memory type m e f : m a s k r o m v e r s i o n : e p r o m o r o n e t i m e p r o m v e r s i o n : f l a s h m e m o r y v e r s i o n ram size 0 1 2 3 4 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes a : high-speed version is omitted in the one time prom version shipped in blank, the eprom version and the flash memory version. 9 : 3 6 8 6 4 b y t e s : 4 0 9 6 0 b y t e s : 4 5 0 5 6 b y t e s : 4 9 1 5 2 b y t e s : 5 3 2 4 8 b y t e s : 5 7 3 4 4 b y t e s : 6 1 4 4 0 b y t e s a b c d e f 5 6 7 8 9 : 7 6 8 b y t e s : 8 9 6 b y t e s : 1 0 2 4 b y t e s : 1 5 3 6 b y t e s : 2 0 4 8 b y t e s
3886 group user s manual hardware group expansion mitsubishi plans to expand the 3886 group as follows. memory type support for mask rom, one time prom, eprom and flash memory version. memory size rom size ........................................................... 32 k to 60 k bytes ram size ......................................................... 1024 to 2048 bytes packages 80p6q-a ................................. 0.5 mm-pitch plastic molded lqfp 80p6s-a .................................. 0.65mm-pitch plastic molded qfp 80d0 ....................... 0.8 mm-pitch ceramic lcc (eprom version) the pin number and the position of the function pin may change by the kind of package. fig. 6 memory expansion plan currently products are listed below. ram size (bytes) remarks package table 3 support products product name as of sep. 2000 32768 (32638) 49152 (49022) 61440 (61310) (p) rom size (bytes) rom size for user in ( ) memory expansion m3886 7m8a-xxxhp m3886 7e8a-xxxhp m3886 7e8ahp m3886 7e8afs m3886 9m8a-xxxhp m3886 9m8a-xxxgp m3886 9mca-xxxhp m3886 9mca-xxxgp m3886 9mfa-xxxhp m3886 9mfa-xxxgp m3886 9ffahp m3886 9ffagp 1024 2048 80p6q-a 80d0 80p6q-a 80p6s-a 80p6q-a 80p6s-a 80p6q-a 80p6s-a 80p6q-a 80p6s-a mask rom version one time prom version one time prom version (blank) eprom version mask rom version flash memory version group expansion m 3886 7 e 8 a / m 8 a 4 8 k r o m s i z e ( b y t e s ) 3 2 k 2 8 k 2 4 k 20 k 16 k 1 2 k 8 k 3 8 45 1 26 4 01 4 0 8 768 89 6 1 0 2 41 1 5 2 1 2 8 0 1 5 3 6 2 0 4 8307 2 403 2 6 0 k r o m e x t e r n a l ram s i ze (b ytes ) : m a s s p r o d u c t i o n m 3 8 8 6 9 f f a / m f a m 3 8 8 6 9 m c a m 3 8 8 6 9 m 8 a / m c a
3886 group user s manual functional description functional description central processing unit (cpu) the 3886 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 6. store registers other than those described in figure 6 with pro- gram when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 7 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
3886 group user s manual hardware table 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 8 register push and pop at interrupt generation and subroutine call functional description n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) execute rts (pc l )m (s) ( s ) ( s ) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 (pc h )m (s) s u b r o u t i n e pop return address from stack p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) 1 (s) (s) + 1 interrupt service routine p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) 1 m ( s )( p c l ) ( s ) ( s ) 1 ( p c l )m ( s ) (s) (s) + 1 ( s ) ( s ) + 1 (pc h )m (s) pop return address from stack i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
3886 group user s manual [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag z flag i flag d flag b flag t flag v flag n flag sec clc _ _ sei cli sed cld _ _ set clt clv _ _ _ functional description functional description
3886 group user s manual hardware [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit, the processor mode bits specifying the chip operation mode, etc. the cpu mode register is allocated at address 003b 16 . fig. 9 structure of cpu mode register functional description p r o c e s s o r m o d e b i t s b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : m e m o r y e x p a n s i o n m o d e ( n o t e ) 1 0 : m i c r o p r o c e s s o r m o d e ( n o t e ) 1 1 : n o t a v a i l a b l e p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n x c o u t o s c i l l a t i n g f u n c t i o n m a i n c l o c k ( x i n x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 7 b 6 0 0 : n o t e : t h i s m o d e i s n o t a v a i l a b l e f o r m 3 8 8 6 9 m 8 a / m c a / m f a a n d t h e f l a s h m e m o r y v e r s i o n . 1 c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0 s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e f i x t h i s b i t t o 1 .
3886 group user s manual memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. pro- gram/erase of the reserved rom area is possible in the eprom version and the flash memory version. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 10 memory map diagram functional description 0100 16 0 0 0 0 1 6 0040 16 ff00 16 f f d c 1 6 fffe 16 ffff 16 1 9 2 2 5 6 3 8 4 5 1 2 6 4 0 7 6 8 8 9 6 1 0 2 4 1 5 3 6 2 0 4 8 x x x x 1 6 0 0 f f 1 6 0 1 3 f 1 6 0 1 b f 1 6 0 2 3 f 1 6 0 2 b f 1 6 0 3 3 f 1 6 0 3 b f 1 6 0 4 3 f 1 6 0 6 3 f 1 6 0 8 3 f 1 6 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 yyyy 16 zzzz 16 ram r o m 0ffe 16 0 f f f 1 6 sfr area n o t u s e d interrupt vector area rom area reserved rom area (note 2) (128 bytes) zero page special page r a m a r e a r a m s i z e ( b y t e s ) a d d r e s s x x x x 1 6 r o m s i z e ( b y t e s ) a d d r e s s y y y y 1 6 reserved rom are a (note 2) a d d r e s s z z z z 1 6 sfr area (note 1) n o t e s 1 : t h i s a r e a i s s f r i n m 3 8 8 6 9 f f a . t h i s a r e a i s r e s e r v e d i n m 3 8 8 6 9 m f a / m c a / m 8 a . t h i s a r e a i s n o t u s e d i n m 3 8 8 6 7 m 8 a / e 8 a . 2 : t h i s a r e a i s u sa b l e i n e p r o m v e r s i o n a n d f l a s h m e m o r y v e r s i o n .
3886 group user s manual hardware fig. 11 memory map of special function register (sfr) functional description 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 0 1 6 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0 0 3 4 1 6 0 0 3 5 1 6 0 0 3 6 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 serial i/o2 register (sio2) port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) port p8 (p8)/port p4 input register (p4i) transmit/receive buffer register (tb/rb) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) serial i/o2 control register (sio2con) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 ) p r e s c a l e r y ( p r e y ) t i m e r y ( t y ) a d / d a c o n t r o l r e g i s t e r ( a d c o n ) d - a 1 c o n v e r s i o n r e g i s t e r ( d a 1 ) d - a 2 c o n v e r s i o n r e g i s t e r ( d a 2 ) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) p r e s c a l e r 1 2 ( p r e 1 2 ) t i m e r 2 ( t 2 ) p r e s c a l e r x ( p r e x ) t i m e r x ( t x ) t i m e r 1 ( t 1 ) t i m e r x y m o d e r e g i s t e r ( t m ) i 2 c data shift register (s0) i 2 c address register (s0d) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) d a t a b u s b u f f e r r e g i s t e r 0 ( d b b 0 ) d a t a b u s b u f f e r s t a t u s r e g i s t e r 0 ( d b b s t s 0 ) d a t a b u s b u f f e r c o n t r o l r e g i s t e r ( d b b c o n ) d a t a b u s b u f f e r r e g i s t e r 1 ( d b b 1 ) d a t a b u s b u f f e r s t a t u s r e g i s t e r 1 ( d b b s t s 1 ) c o m p a r a t o r d a t a r e g i s t e r ( c m p d ) p o r t c o n t r o l r e g i s t e r 1 ( p c t l 1 ) p o r t c o n t r o l r e g i s t e r 2 ( p c t l 2 ) p w m 0 h r e g i s t e r ( p w m 0 h ) p w m 0 l r e g i s t e r ( p w m 0 l ) p w m 1 h r e g i s t e r ( p w m 1 h ) p w m 1 l r e g i s t e r ( p w m 1 l ) a - d c o n v e r s i o n r e g i s t e r 2 ( a d 2 ) i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( i n t s e l ) watchdog timer control register (wdtcon) 0 f f e 1 6 0 f f f 1 6 f l a s h c o m m a n d r e g i s t e r ( f c m d ) f l a s h m e m o r y c o n t r o l r e g i s t e r ( f c o n ) ( n o t e ) ( n o t e ) note: only for flash memory version p o r t p 8 d i r e c t i o n r e g i s t e r ( p 8 d ) / p o r t p 7 i n p u t r e g i s t e r ( p 7 i )
3886 group user s manual pin name input/output i/o structure non-port function ref.no. table 6 i/o port function (1) related sfrs i/o ports the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin becomes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. when the p8 function select bit of the port control register 2 (ad- dress 002f 16 ) is set to 1 , read from address 0010 16 becomes the port p4 input register, and read from address 0011 16 becomes the port p7 input register. as the particular function, value of p4 2 to p4 6 pins and p7 0 to p7 5 pins can be read regardless of setting direction registers, by read- ing the port p4 input register (address 0010 16 ) or the port p7 input register (address 0011 16 ) respectively. p0 0 /p3 ref p0 1 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 /pwm 00 p3 1 /pwm 10 p3 2 p3 7 p4 0 /x cout p4 1 /x cin p4 2 /int 0 / obf 00 p4 3 /int 1 / obf 01 p4 4 /r x d p4 5 /t x d p4 6 /s clk1 /obf 10 p4 7 /s rdy1 /s 1 port p0 port p1 port p2 port p3 port p4 input/output, individual bits cmos compatible input level cmos 3-state output or n-channel open- drain output cmos compatible input level cmos 3-state output cmos compatible input level or ttl input level cmos 3-state output or n-channel open- drain output address low-order byte output analog comparator power source input pin address low-order byte output address high-order byte output data bus i/o control signal i/o pwm output key-on wake up input comparator input control signal i/o key-on wake up input comparator input sub-clock generating circuit external interrupt input bus interface function i/o serial i/o1 function in- put serial i/o1 function out- put serial i/o1 function i/o bus interface function output serial i/o1 function out- put bus interface function input cpu mode register port control register 1 serial i/o2 control register cpu mode register port control register 1 cpu mode register cpu mode register port control register 1 ad/da control register cpu mode register port control register 1 cpu mode register interrupt edge selection register port control register 2 data bus buffer control register serial i/o1 control register port control register 2 serial i/o1 control register uart control register port control register 2 serial i/o1 control register data bus buffer control register port control register 2 serial i/o1 control register data bus buffer control register (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) cmos compatible input level cmos 3-state output (when selecting bus interface function) cmos compatible input level or ttl input level functional description
3886 group user s manual hardware notes1 : for details of the functions of ports p0 to p3 in modes other than single-chip mode, and how to use double-function ports as f unction i/o ports, refer to the applicable sections. 2 : make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate. pin name input/output i/o format non-port function ref.no. table 7 i/o port function (2) related sfrs p5 0 /a 0 p5 1 /int 20 /s 0 p5 2 /int 30 /r p5 3 /int 40 /w p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /da 1 / pwm 01 p5 7 /da 2 / pwm 11 p6 0 /an 0 p6 7 /an 7 p7 0 /s in2 p7 1 /s out2 p7 2 /s clk2 p7 3 /s rdy2 / int 21 p7 4 /int 31 p7 5 /int 41 p7 6 /s da p7 7 /s cl p8 0 /dq 0 p8 7 /dq 7 port p5 port p6 port p7 port p8 input/output, individual bits cmos compatible input level cmos 3-state output (when selecting bus interface function) cmos compatible input level or ttl input level cmos compatible input level cmos 3-state output cmos compatible input level or ttl input level n-channel open-drain output cmos compatible input level n-channel open-drain output (when selecting i 2 c- bus interface function) cmos compatible input level or smbus input level cmos compatible input level cmos 3-state output (when selecting bus interface function) cmos compatible input level or ttl input level bus interface function input external interrupt input bus interface function input timer x, timer y func- tion i/o d-a converter output pwm output a-d converter input serial i/o2 function i/o serial i/o2 function out- put bus interface function input external interrupt input i 2 c-bus interface func- tion i/o bus interface function i/o data bus buffer control register interrupt edge selection register data bus buffer control register timer xy mode register ad/da control register uart control register ad/da control register serial i/o2 control register port control register 2 serial i/o2 control register port control register 2 interrupt edge selection register port control register 2 i 2 c control register data bus buffer control register (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) functional description
3886 group user s manual fig. 12 port block diagram (1) functional description ( 2 ) p o r t s p 0 1 p 0 7 , p 1 data bus p o r t l a t c h output structur e selection bit s ( 3 ) p o r t p 2 data bus port latch ( 4 ) p o r t p 3 0 comparator k e y - o n w a k e - u p p3 0 p3 3 pull-up control bit i n p u t data bus port latch pwm 00 outpu t pwm 0 output pin selection bit p w m 0 e n a b l e b i t (5) port p3 1 p3 0 p3 3 pull-up control bi t data bus port latch pwm 10 outpu t pwm 1 output pin selection bit p w m 1 e n a b l e b i t ( 6 ) p o r t s p 3 2 p 3 7 (7) port p4 0 port x c switch bi t o s c i l l a t o r port p4 1 p o r t x c s w i t c h b i t (8) port p4 1 sub-clock generating circuit inpu t ( 1 ) p o r t p 0 0 d a t a b u s p o r t l a t c h p0 0 p0 3 output structure selection bi t c o m p a r a t o r r e f e r e n c e p o w e r s o u r c e i n p u t c o m p a r a t o r r e f e r e n c e i n p u t p i n s e l e c t b i t p0 0 p0 3 , p0 4 p0 7 , p1 0 p1 3 , p1 4 p1 7 pull-up control bi t p3 0 p3 3 , p3 4 p3 7 c o m p a r a t o r k e y - o n w a k e - u p i n p u t data bus p o r t l a t c h comparator k e y - o n w a k e - u p input data bus port latch port x c switch bit d a t a b u s port latch d i r e c t i o n r e g i s t e r direction register d i r e c t i o n r e g i s t e r d i r e c t i o n r e g i s t e r direction register d i r e c t i o n r e g i s t e r d i r e c t i o n r e g i s t e r direction register
3886 group user s manual hardware fig. 13 port block diagram (2) functional description serial i/o1 input ( 1 1 ) p o r t p 4 4 d a t a b u s s e r i a l i / o 1 e n a b l e b i t r e c e i v e e n a b l e b i t p o r t l a t c h p 4 o u t p u t s t r u c t u r e s e l e c t i o n b i t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
3886 group user s manual fig. 14 port block diagram (3) functional description (20) port p6 a n a l o g i n p u t p i n s e l e c t i o n b i t a - d c o n v e r t e r i n p u t data bu s p o r t l a t c h d i r e c t i o n r e g i s t e r (18) port p5 6 d - a c o n v e r t e r o u t p u t d-a 1 output enable bit data bu s p o r t l a t c h direction re g ister p w m 0 1 o u t p u t pwm 0 output pin selection bit p w m 0 e n a b l e b i t ( 1 9 ) p o r t p 5 7 d - a c o n v e r t e r o u t p u t d-a 2 output enable bit data bu s port latch d i r e c t i o n r e g i s t e r pwm 11 output p w m 1 o u t p u t p i n s e l e c t i o n b i t pwm 1 enable bi t ( 1 7 ) p o r t s p 5 4 , p 5 5 p o r t l a t c h d a t a b u s p u l s e o u t p u t m o d e t i m e r o u t p u t c n t r 0 , c n t r 1 i n t e r r u p t i n p u t d i r e c t i o n r e g i s t e r ( 2 1 ) p o r t p 7 0 serial i/o2 input data bu s p o r t l a t c h d i r e c t i o n r e g i s t e r ? ? ? ? ? ? ? ? ? ?
3886 group user s manual hardware fig. 15 port block diagram (4) functional description ( 2 8 ) p o r t p 8 output buffer 0 s t a t u s r e g i s t e r 0 output buffer 1 s t a t u s r e g i s t e r 1 i n p u t b u f f e r 0 i n p u t b u f f e r 1 d a t a b u s b u f f e r e n a b l e b i t ( 2 6 ) p o r t p 7 6 data bus p o r t l a t c h d i r e c t i o n r e g i s t e r s d a o u t p u t s d a i n p u t ? ? ? ? ? ? ?
3886 group user s manual fig. 16 structure of port i/o related register functional description p o r t c o n t r o l r e g i s t e r 1 b7 b0 p o r t c o n t r o l r e g i s t e r 2 p0 0 p0 3 output structure selection bit 0: cmos 1: n-channel open-drain p0 4 p0 7 output structure selection bit 0: cmos 1: n-channel open-drain p1 0 p1 3 output structure selection bit 0: cmos 1: n-channel open-drain p1 4 p1 7 output structure selection bit 0: cmos 1: n-channel open-drain p3 0 p3 3 pull-up control bit 0: no pull-up 1: pull-up p3 4 p3 7 pull-up control bit 0: no pull-up 1: pull-up pwm 0 enable bit 0: pwm 0 output disabled 1: pwm 0 output enabled pwm 1 enable bit 0: pwm 1 output disabled 1: pwm 1 output enabled p4 input level selection bit (p4 2 p4 6 ) 0: cmos level input 1: ttl level input p7 input level selection bit (p7 0 p7 5 ) 0: cmos level input 1: ttl level input p4 output structure selection bit (p4 2 , p4 3 , p4 4 , p4 6 ) 0: cmos 1: n-channel open-drain p8 function selection bit 0: port p8/port p8 direction register 1: port p4 input register/port p7 input register int 2 , int 3 , int 4 interrupt switch bit 0: int 20 , int 30 , int 40 interrupt 1: int 21 , int 31 , int 41 interrupt timer y count source selection bit 0: f(x in )/16 (f(x cin )/16 in low-speed mode) 1: f(x cin ) oscillation stabilizing time set after stp instruction released bit 1: no automatic set port output p4 2 /p4 3 clear function selection bit 0: only software clear 1: software clear and output data bus buffer 0 reading (system bus side) b7 b0 ( p c t l 1 : a d d r e s s 0 0 2 e 1 6 ) ( p c t l 2 : a d d r e s s 0 0 2 f 1 6 ) 0 : a u t o m a t i c s e t 0 1 1 6 t o t i m e r 1 a n d f f 1 6 t o p r e s c a l e r 1 2
3886 group user s manual hardware interrupts interrupts occur by 16 sources among 21 sources: nine external, eleven internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the in- terrupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts except the brk in- struction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. interrupt source selection any of the following interrupt sources can be selected by the inter- rupt source selection register (address 0039 16 ). 1. int 0 or input buffer full 2. int 1 or output buffer empty 3. serial i/o1 transmission or s cl s da 4. cntr 0 or s cl s da 5. serial i/o2 or i 2 c 6. int 2 or i 2 c 7. cntr 1 or key-on wake-up 8. a-d conversion or key-on wake-up external interrupt pin selection the occurrence sources of the external interrupt int 2 , int 3 , and int 4 can be selected from either input from int 20 , int 30 , int 40 pin, or input from int 21 , int 31 , int 41 pin by the int 2 , int 3 , int 4 interrupt switch bit (bit 4 of address 002f 16 ). notes when setting of the following register or bit is changed, the inter- rupt request bit may be set to 1. interrupt edge selection register (address 003a 16 ) interrupt source selection register (address 0039 16 ) int 2 , int 3 , int 4 interrupt switch bit of p ort control register 2 (bit 4 of address 002f 16 ) accept the interrupt after clearing the interrupt request bit to 0 af- ter interrupt is disabled and the above register or bit is set. functional description
3886 group user s manual interrupt request generating conditions remarks interrupt source low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 table 8 interrupt vector addresses and priority notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) reset (note 2) int 0 input buffer full (ibf) int 1 output buffer empty (obe) serial i/o1 reception serial i/o1 transmission s cl , s da timer x timer y timer 1 timer 2 cntr 0 s cl , s da cntr 1 key-on wake-up serial i/o2 i 2 c int 2 i 2 c int 3 int 4 a-d converter key-on wake-up brk instruction at reset at detection of either rising or falling edge of int 0 input at input data bus buffer writing at detection of either rising or falling edge of int 1 input at output data bus buffer read- ing at completion of serial i/o1 data reception at completion of serial i/o1 transfer shift or when transmis- sion buffer is empty at detection of either rising or falling edge of s cl or s da at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of s cl or s da at detection of either rising or falling edge of cntr 1 input at falling of port p3 (at input) in- put logical level and at completion of serial i/o2 data transfer at completion of data transfer at detection of either rising or falling edge of int 2 input at completion of data transfer at detection of either rising or falling edge of int 3 input at detection of either rising or falling edge of int 4 input at completion of a-d conversion at falling of port p3 (at input) in- put logical level and at brk instruction execution non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o1 is selected valid when serial i/o1 is selected external interrupt (active edge selectable) stp release timer underflow external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (falling edge valid) valid when serial i/o2 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (falling edge valid) non-maskable software interrupt functional description
3886 group user s manual hardware fig. 17 interrupt control fig. 18 structure of interrupt-related registers (1) functional description i n t e r r u p t d i s a b l e f l a g ( i ) i n t e r r u p t r e q u e s t i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t b r k i n s t r u c t i o n r e s e t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 a c t i v e e d g e s e l e c t i o n b i t i n t 1 a c t i v e e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) i n t 2 a c t i v e e d g e s e l e c t i o n b i t i n t 3 a c t i v e e d g e s e l e c t i o n b i t i n t 4 a c t i v e e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( i n t e d g e : a d d r e s s 0 0 3 a 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t r e q u e s t b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r y i n t e r r u p t r e q u e s t b i t t i m e r 1 i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t interrupt control register 1 i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t e n a b l e b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r y i n t e r r u p t e n a b l e b i t t i m e r 1 i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 ) (icon1 : address 003e 16 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 cntr 0 /s cl , s da interrupt request bit cntr 1 /key-on wake-up interrupt request bit serial i/o2/i 2 c interrupt request bit int 2 /i 2 c interrupt request bit int 3 interrupt request bit int 4 interrupt request bit ad converter/key-on wake-up interrupt request bit not used (returns 0 when read) ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 ) interrupt control register 2 cntr 0 /s cl , s da interrupt enable bit cntr 1 /key-on wake-up interrupt enable bit serial i/o2/i 2 c interrupt enable bit int 2 /i 2 c interrupt enable bit int 3 interrupt enable bit int 4 interrupt enable bit ad converter/key-on wake-up interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit) 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d (icon2 : address 003f 16 ) 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b7 b0
3886 group user s manual fig. 19 structure of interrupt-related registers (2) functional description b 7 b 0 i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 0 i n t e r r u p t 1 : i n p u t b u f f e r f u l l i n t e r r u p t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 1 i n t e r r u p t 1 : o u t p u t b u f f e r e m p t y i n t e r r u p t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : s e r i a l i / o 1 t r a n s m i t i n t e r r u p t 1 : s c l , s d a i n t e r r u p t c n t r 0 / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : c n t r 0 i n t e r r u p t 1 : s c l , s d a i n t e r r u p t s e r i a l i / o 2 / i 2 c i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : s e r i a l i / o 2 i n t e r r u p t 1 : i 2 c i n t e r r u p t i n t 2 / i 2 c i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 2 i n t e r r u p t 1 : i 2 c i n t e r r u p t c n t r 1 / k e y - o n w a k e - u p i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : c n t r 1 i n t e r r u p t 1 : k e y - o n w a k e - u p i n t e r r u p t a d c o n v e r t e r / k e y - o n w a k e - u p i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : a - d c o n v e r t e r i n t e r r u p t 1 : k e y - o n w a k e - u p i n t e r r u p t i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ) (do not write 1 to these bits simultaneously.) (do not write 1 to these bits simultaneously.) (intsel: address 0039 16 )
3886 group user s manual hardware key input interrupt (key-on wake up) a key input interrupt request is generated by applying l level to any pin of port p3 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 20, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p3 0 p3 3 . fig. 20 connection example when using key input interrupt and port p3 block diagram functional description ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? 0 p o r t p 3 1 l a t c h port p3 1 direction register = 0 p o r t p 3 2 l a t c h port p3 2 direction register = 0 port p3 3 latch p o r t p 3 3 d i r e c t i o n r e g i s t e r = 0 port p3 4 latch p o r t p 3 4 d i r e c t i o n r e g i s t e r = 1 p o r t p 3 5 l a t c h p o r t p 3 5 d i r e c t i o n r e g i s t e r = 1 p o r t p 3 6 l a t c h p o r t p 3 6 d i r e c t i o n r e g i s t e r = 1 p o r t p 3 7 l a t c h p o r t p 3 7 d i r e c t i o n r e g i s t e r = 1 p 3 0 i n p u t p3 1 input p3 2 input p3 3 input p3 4 output p3 5 output p3 6 output p3 7 output p o r t c o n t r o l r e g i s t e r 1 b i t 5 = 1 p o r t p 3 i n p u t r e a d i n g c i r c u i t c o m p a r a t o r c i r c u i t p o r t p x x l l e v e l o u t p u t ? ?? 1
3886 group user s manual timers the 3886 group has four timers: timer x, timer y, timer 1, and timer 2. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are count down. when the timer reaches 00 16 , an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1 . timer 1 and timer 2 the count source of prescaler 12 is the oscillation frequency di- vided by 16. the output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. timer x and timer y timer x and timer y can each select in one of four operating modes by setting the timer xy mode register. (1) timer mode the timer counts f(x in )/16. (2) pulse output mode timer x (or timer y) counts f(x in )/16. whenever the contents of the timer reach 00 16 , the signal output from the cntr 0 (or cntr 1 ) pin is inverted. if the cntr 0 (or cntr 1 ) active edge se- lection bit is 0 , output begins at h . if it is 1 , output starts at l . when using a timer in this mode, set the corresponding port p5 4 ( or port p5 5 ) direction register to out- put mode. (3) event counter mode operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the cntr 0 or cntr 1 pin. when the cntr 0 (or cntr 1 ) active edge selection bit is 0 , the rising edge of the cntr 0 (or cntr 1 ) pin is counted. when the cntr 0 (or cntr 1 ) active edge selection bit is 1 , the falling edge of the cntr 0 (or cntr 1 ) pin is counted. (4) pulse width measurement mode if the cntr 0 (or cntr 1 ) active edge selection bit is 0 , the timer counts f(x in )/16 while the cntr 0 (or cntr 1 ) pin is at h . if the cntr 0 (or cntr 1 ) active edge selection bit is 1 , the timer counts while the cntr 0 (or cntr 1 ) pin is at l . the count can be stopped by setting 1 to the timer x (or timer y) count stop bit in any mode. the corresponding interrupt request bit is set each time a timer overflows. the count source for timer y in the timer mode or the pulse output mode can be selected from either f(x in )/16 or f(x cin ) by the timer y count source selection bit of the port control register 2 (bit 5 of address 002f 16 ). fig. 21 structure of timer xy mode register functional description timer x count stop bit 0: count start 1: count stop t i m e r x y m o d e r e g i s t e r ( t m : a d d r e s s 0 0 2 3 1 6 ) t i m e r y o p e r a t i n g m o d e b i t 0 0 : t i m e r m o d e 0 1 : p u l s e o u t p u t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 1 a c t i v e e d g e s e l e c t i o n b i t 0 : i n t e r r u p t a t f a l l i n g e d g e c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e 1 : i n t e r r u p t a t r i s i n g e d g e c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e b7 c n t r 0 a c t i v e e d g e s e l e c t i o n b i t 0 : i n t e r r u p t a t f a l l i n g e d g e c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e 1 : i n t e r r u p t a t r i s i n g e d g e c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e b 0 t i m e r x o p e r a t i n g m o d e b i t 0 0 : t i m e r m o d e 0 1 : p u l s e o u t p u t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h m e a s u r e m e n t m o d e b1b0 b 5 b 4 timer y count stop bit 0: count start 1: count stop
3886 group user s manual hardware fig. 22 block diagram of timer x, timer y, timer 1, and timer 2 functional description q q 1 0 p 5 4 / c n t r 0 q q p5 5 /cntr 1 1 / 1 6 f ( x i n ) 0 1 r r 1 0 0 1 t t p r e s c a l e r x l a t c h ( 8 ) p r e s c a l e r x ( 8 ) timer x latch (8) timer x (8) t o t i m e r x i n t e r r u p t r e q u e s t b i t t o g g l e f l i p - f l o p t i m e r x c o u n t s t o p b i t p u l s e w i d t h m e a s u r e m e n t m o d e e v e n t c o u n t e r m o d e t o c n t r 0 i n t e r r u p t r e q u e s t b i t p u l s e o u t p u t m o d e p o r t p 5 4 l a t c h port p5 4 direction register c n t r 0 a c t i v e e d g e s e l e c t i o n b i t t i m e r x l a t c h w r i t e p u l s e p u l s e o u t p u t m o d e t i m e r m o d e p u l s e o u t p u t m o d e p r e s c a l e r y l a t c h ( 8 ) p r e s c a l e r y ( 8 ) timer y latch (8) t i m e r y ( 8 ) to timer y interrupt request bit t o g g l e f l i p - f l o p t i m e r y c o u n t s t o p b i t to cntr 1 interrupt request bit pulse output mode port p5 5 latch port p5 5 direction register c n t r 1 a c t i v e e d g e s e l e c t i o n b i t timer y latch write pulse pulse output mode timer mode pulse output mod e data bus d a t a b u s d i v i d e r o s c i l l a t o r p r e s c a l e r 1 2 l a t c h ( 8 ) p r e s c a l e r 1 2 ( 8 ) timer 1 latch (8) t i m e r 1 ( 8 ) data bus t i m e r 2 l a t c h ( 8 ) timer 2 (8) t o t i m e r 2 i n t e r r u p t r e q u e s t b i t t o t i m e r 1 i n t e r r u p t r e q u e s t b i t c n t r 0 a c t i v e e d g e s e l e c t i o n b i t c n t r 1 a c t i v e e d g e s e l e c t i o n b i t pulse width measure- ment mode e v e n t c o u n t e r m o d e 1 / 1 6 f ( x i n ) d i v i d e r o s c i l l a t o r 1/16 f(x in ) divider oscillator f ( x c i n ) oscillator 0 1 t i m e r y c o u n t s o u r c e s e l e c t i o n b i t ( f ( x c i n ) i n l o w - s p e e d m o d e ) ( f ( x c i n ) i n l o w - s p e e d m o d e ) (f(x cin ) in low-speed mode)
3886 group user s manual serial i/o serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6 of address 001a 16 ) to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. fig. 23 block diagram of clock synchronous serial i/o1 fig. 24 operation of clock synchronous serial i/o1 function functional description 1 / 4 1 / 4 f / f p 4 6 / s c l k 1 / o b f 1 0 s e r i a l i / o 1 s t a t u s r e g i s t e r s e r i a l i / o 1 c o n t r o l r e g i s t e r p 4 7 / s r d y 1 / s 1 p 4 4 / r x d p 4 5 / t x d f ( x i n ) r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) c l o c k c o n t r o l c i r c u i t s h i f t c l o c k s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) b a u d r a t e g e n e r a t o r a d d r e s s 0 0 1 c 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t f a l l i n g - e d g e d e t e c t o r t r a n s m i t b u f f e r r e g i s t e r d a t a b u s a d d r e s s 0 0 1 8 1 6 s h i f t c l o c k t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t a d d r e s s 0 0 1 9 1 6 d a t a b u s a d d r e s s 0 0 1 a 1 6 t r a n s m i t s h i f t r e g i s t e r ( f ( x c i n ) i n l o w - s p e e d m o d e ) d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 t b e = 0 t b e = 1 t s c = 0 t r a n s f e r s h i f t c l o c k ( 1 / 2 t o 1 / 2 0 4 8 o f t h e i n t e r n a l c l o c k , o r a n e x t e r n a l c l o c k ) s e r i a l o u t p u t t x d s e r i a l i n p u t r x d w r i t e p u l s e t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 1 8 1 6 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n n o t e s 1 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h i c h c a n b e s e l e c t e d , e i t h e r w h e n t h e t r a n s m i t b u f f e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . r e c e i v e e n a b l e s i g n a l s r d y 1
3886 group user s manual hardware (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit of the serial i/o1 control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 25 block diagram of uart serial i/o1 functional description f ( x i n ) 1 / 4 oe p ef e 1 / 1 6 1/16 data bus receive buffer register address 0018 16 r e c e i v e s h i f t r e g i s t e r receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) a d d r e s s 0 0 1 c 1 6 s t / s p / p a g e n e r a t o r transmit buffer register data bus transmit shift register a d d r e s s 0 0 1 8 1 6 t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) transmit interrupt request (ti) address 0019 16 st detector s p d e t e c t o r uart control register a d d r e s s 0 0 1 b 1 6 character length selection bit address 001a 16 b r g c o u n t s o u r c e s e l e c t i o n b i t transmit interrupt source selection bit serial i/o1 synchronous clock selection bit c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s serial i/o1 control register p4 6 /s clk1 /obf 10 s e r i a l i / o 1 s t a t u s r e g i s t e r p 4 4 / r x d p4 5 /t x d ( f ( x c i n ) i n l o w - s p e e d m o d e )
3886 group user s manual fig. 26 operation of uart serial i/o1 function [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the p4 5 /t x d pin. [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1 , the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. functional description t s c = 0 t b e = 1 rbf=0 t b e = 0t b e = 0 r b f = 1 rbf=1 s t d 0 d 1 s p d 0 d 1 s t s p tbe=1 t s c = 1 s t d 0 d 1 s p d 0 d 1 s t s p t r a n s m i t o r r e c e i v e c l o c k t r a n s m i t b u f f e r w r i t e s i g n a l g e n e r a t e d a t 2 n d b i t i n 2 - s t o p - b i t m o d e 1 s t a r t b i t 7 o r 8 d a t a b i t 1 o r 0 p a r i t y b i t 1 o r 2 s t o p b i t ( s ) 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 , c a n b e s e l e c t e d t o o c c u r d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . 4 : a f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r w h e n t s c = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o t s c = 0 . n o t e s ? ?
3886 group user s manual hardware b 7 b 7 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o 1 s t a t u s r e g i s t e r s e r i a l i / o 1 c o n t r o l r e g i s t e r b 0 b 0 b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) ( f ( x c i n ) i n l o w - s p e e d m o d e ) 1 : f ( x i n ) / 4 ( f ( x c i n ) / 4 i n l o w - s p e e d m o d e ) s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y 1 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 4 7 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 4 7 p i n o p e r a t e s a s s r d y 1 o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o 1 m o d e s e l e c t i o n b i t ( s i o m ) 0 : c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 1 e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o d i s a b l e d ( p i n s p 4 4 t o p 4 7 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o e n a b l e d ( p i n s p 4 4 t o p 4 7 o p e r a t e a s s e r i a l i / o p i n s ) b7 uart control register character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return 1 when read) b0 ( s i o 1 s t s : a d d r e s s 0 0 1 9 1 6 ) ( s i o 1 c o n : a d d r e s s 0 0 1 a 1 6 ) (uartcon : address 001b 16 ) fig. 27 structure of serial i/o1 control registers functional description
3886 group user s manual serial i/o2 the serial i/o2 function can be used only for clock synchronous serial i/o. for clock synchronous serial i/o the transmitter and the receiver must use the same clock. if the internal clock is used, transfer is started by a write signal to the serial i/o2 register. [serial i/o2 control register (sio2con)] 001d 16 the serial i/o2 control register contains seven bits which control various serial i/o functions. fig. 28 structure of serial i/o2 control register fig. 29 block diagram of serial i/o2 function functional description s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n : a d d r e s s 0 0 1 d 1 6 ) b 7 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s 0 0 0 : f ( x i n ) / 8 ( f ( x c i n ) / 8 i n l o w - s p e e d m o d e ) 0 0 1 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) 0 1 0 : f ( x i n ) / 3 2 ( f ( x c i n ) / 3 2 i n l o w - s p e e d m o d e ) 0 1 1 : f ( x i n ) / 6 4 ( f ( x c i n ) / 6 4 i n l o w - s p e e d m o d e ) 1 1 0 : f ( x i n ) / 1 2 8 ( f ( x c i n ) / 1 2 8 i n l o w - s p e e d m o d e ) 1 1 1 : f ( x i n ) / 2 5 6 ( f ( x c i n ) / 2 5 6 i n l o w - s p e e d m o d e ) s e r i a l i / o 2 p o r t s e l e c t i o n b i t 0 : i / o p o r t 1 : s o u t 2 , s c l k 2 s i g n a l o u t p u t s r d y 2 o u t p u t e n a b l e b i t 0 : i / o p o r t 1 : s r d y 2 s i g n a l o u t p u t t r a n s f e r d i r e c t i o n s e l e c t i o n b i t 0 : l s b f i r s t 1 : m s b f i r s t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k c o m p a r a t o r r e f e r e n c e i n p u t s e l e c t i o n b i t 0 : p 0 0 / p 3 r e f i n p u t 1 : r e f e r e n c e i n p u t f i x e d b 0 b 2 b 1 b 0 x in 1 0 0 1 0 1 s r d y 2 s c l k 2 0 1 1/8 1/16 1/32 1/64 1/128 1/256 x c i n 10 0 0 0 1 d a t a b u s serial i/o2 interrupt request serial i/o2 port selection bit serial i/o counter 2 (3) serial i/o2 register (8) s y n c h r o n i z a t i o n c i r c u i t s e r i a l i / o 2 p o r t s e l e c t i o n b i t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s rdy2 output enable bit external cloc k internal synchronous clock selection bits d i v i d e r p7 2 /s clk2 p7 1 /s out2 p7 0 /s in2 p7 2 latch p7 1 latch p 7 3 l a t c h p7 3 /s rdy2 /int 21 m a i n c l o c k d i v i d e r a t i o s e l e c t i o n b i t s ( n o t e ) n o t e : t h e s e b i t s s e l e c t a n y o f t h e h i g h - s p e e d m o d e , t h e m i d d l e - s p e e d m o d e , a n d t h e l o w - s p e e d m o d e . t h e s e a r e a s s i g n e d t o b i t s 7 a n d 6 o f t h e c p u m o d e r e g i s t e r ( a d d r e s s 0 0 3 b 1 6 ) .
3886 group user s manual hardware fig. 30 timing of serial i/o2 function functional description d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 t r a n s f e r c l o c k ( n o t e 1 ) s e r i a l i / o 2 o u t p u t s o u t 2 s e r i a l i / o 2 i n p u t s i n 2 r e c e i v e e n a b l e s i g n a l s r d y 2 s e r i a l i / o 2 r e g i s t e r w r i t e s i g n a l ( n o t e 2 ) s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t s e t 1 : w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e t r a n s f e r c l o c k , t h e d i v i d e r a t i o c a n b e s e l e c t e d b y s e t t i n g b i t s 0 t o 2 o f t h e s e r i a l i / o 2 c o n t r o l r e g i s t e r . 2 : w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e t r a n s f e r c l o c k , t h e s o u t 2 p i n g o e s t o h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n . n o t e s
3886 group user s manual pulse width modulation (pwm) output circuit the 3886 group has two pwm output circuits, pwm0 and pwm1, with 14-bit resolution respectively. these can operate indepen- dently. when the oscillation frequency x in is 10 mhz, the minimum resolution bit width is 200 ns and the cycle period is 3276.8 fig. 31 pwm block diagram (pwm0) functional description 1 4 1 / 2 p w m 0 e n a b l e b i t p3 0 latch p 3 0 / p w m 0 0 p w m 0 l r e g i s t e r ( a d d r e s s 0 0 3 1 1 6 ) p w m 0 h r e g i s t e r ( a d d r e s s 0 0 3 0 1 6 ) b i t 7 bit 0 b i t 5 msb lsb pwm 0 bit 7 bit 0 pwm0 timing generator (64 1 a t w r i t e d a t a b u s f ( x i n ) ( 8 m h z ) 1 4 - b i t p w m 0 c i r c u i t p 5 6 d i r e c t i o n r e g i s t e r pwm 0 enable bit p w m 0 e n a b l e b i t p5 6 latch p 5 6 / d a 1 / p w m 0 1 p w m 0 o u t p u t s e l e c t i o n b i t p 3 0 d i r e c t i o n r e g i s t e r (4mhz) pwm 0 enable bit p w m 0 o u t p u t s e l e c t i o n b i t
3886 group user s manual hardware data setup (pwm0) the pwm0 output pin also functions as port p3 0 or p5 6 . the pwm0 output pin is selected from either p3 0 /pwm 00 or p5 6 /pwm 01 by bit 4 of the ad/da control register (address 0034 16 ). the pwm0 output becomes enabled state by setting bit 6 of the port control register 1 (address 002e 16 ). the high-order eight bits of output data are set in the pwm0h register (address 0030 16 ) and the low-order six bits are set in the pwm0l register (address 0031 16 ). pwm1 is set as the same way. pwm operation the 14-bit pwm data is divided into the low-order six bits and the high-order eight bits in the pwm latch. the high-order eight bits of data determine how long an h -level signal is output during each sub-period. there are 64 sub-periods in each period, and each sub-period is 256 ? h for a length equal to n times h or l of the bit in the add part shown in figure 33 is added to this h duration by the contents of the low-order 6-bit data ac- cording to the rule in table 9. that is, only in the sub-period tm shown by table 9 in the pwm cycle period t = 64t, its h duration is lengthened to the mini- mum resolution h - level output in sub-periods t 8 , t 24 , t 32 , t 40 , and t 56 is 4 h level of each sub-period almost becomes equal, because the time becomes length set in the high-order 8 bits or becomes the value plus transfer from register to latch data written to the pwml register is transferred to the pwm latch at each pwm period (every 4096 0 and it is not done when bit 7 is 1. table 9 relationship between low-order 6 bits of data and period set by the add bit low-order 6 bits of data (pwml) lsb 000000 000001 000010 000100 001000 010000 100000 sub-periods tm lengthened (m=0 to 63) none m=32 m=16, 48 m=8, 24, 40, 56 m=4, 12, 20, 28, 36, 44, 52, 60 m=2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m=1, 3, 5, 7, ................................................ ,57, 59, 61, 63 fig. 32 pwm timing functional description 4 0 9 6 h p u l s e w i d t h i s 1 6 . 0 h p u l s e w i d t h i s 1 5 . 7 5
3886 group user? manual fig. 33 14-bit pwm timing (pwm 0 ) functional description 6 a 6 a6 a6a6 a6 b6 a6 a6a6a 6 a6 a6a6 a 6 b6 b6 b6 b6 b6 b6 b6b6b 6 b6 b6b 6 b 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 a 6a 6 b 6 b 6 b 6a 6b 6 b 6 b 6a 6b 6 b 6 b 6 a 6 a 6 a 6a 6 a 6 a 6 a 6a 6 a 6 a 6a 6 a 6 a 6 a 4 3 4 4 3 4 4 3 4 6 b 6 a 69 68 6 7 02 0 1 6 a 6 9 6 8 6 7 02 01 0 2 0 1 0 0 f f f e f d 97 9 6 9 5 02 01 0 0 fc f f f e f d 97 96 95 fc a d d a d d 1 6 5 3 1 6 1 a 9 3 1 6 1aa4 16 1 a a 4 1 6 1ee4 16 1 e f 5 1 6 t = 4096 s ( 6 4 ? 6 4 s ) t = 64 s when bit 7 of pwm0l is 0, transfer from register to latch is disabled. 13 16 a4 16 24 16 3 5 1 6 7 b 1 6 6 a 1 6 5 9 1 6 d a t a 2 4 1 6 s t o r e d a t a d d r e s s 0 0 3 1 1 6 d a t a 6 a 1 6 s t o r e d a t a d d r e s s 0 0 3 0 1 6 d a t a 7 b 1 6 s t o r e d a t a d d r e s s 0 0 3 0 1 6 d a t a 3 5 1 6 s t o r e d a t a d d r e s s 0 0 3 1 1 6 transfer from register to latch t r a n s f e r f r o m r e g i s t e r t o l a t c h b i t 7 c l e a r e d a f t e r t r a n s f e r 6 b 1 6 3 6 t i m e s 6a 16 28 times ( 1 0 7 ) ( 1 0 6 ) 6b 16 24 times 6a 16 40 times t = 64 s (256 ? 0.25 s) m i n i m u m r e s o l u t i o n b i t w i d t h = 0 . 2 5 s h duration length specified by pwm0h 256 (64 s), fixed t h e a d d p o r t i o n s w i t h a d d i t i o n a l t a r e d e t e r m i n e d b y p w m l . pwm0h register pwm0l register p w m 0 l a t c h ( 1 4 b i t s ) e x a m p l e 1 p w m 0 o u t p u t l o w - o r d e r 6 - b i t o u t p u t : h l 6 a 1 6 , 2 4 1 6 e x a m p l e 2 pwm 0 output low-order 6-bit output: h l 6a 16 , 18 16 p w m o u t p u t 8 - b i t c o u n t e r 106 ? 64 + 24 1 2 b 5 1 6 1 0 6 ? 6 4 + 3 6 2
3886 group user s manual hardware bus interface the 3886 group has a 2-byte bus interface function which is al- most functionally equal to melps8-41 series and the control signal from the host cpu side can operate it (slave mode). it is possible to connect the 3886 group with the rd and wr separated cpu bus directly. figure 36 shows the block diagram of the bus interface function. the data bus buffer function i/o pins (p4 2 , p4 3 , p4 6 , p4 7 , p5 0 p5 3 , p8) also function as the normal digital port i/o pins. when bit 0 (data bus buffer enable bit) of the data bus buffer control regis- ter (address 002a 16 ) is 0, these pins become the normal digital port i/o pins. when it is 1, these bits become the data bus buffer function i/o pins. the selection of either the single data bus buffer mode, which uses 1 byte: data bus buffer 0 only, or the double data bus buffer mode, which uses 2 bytes: data bus buffer 0 and data bus buffer 1, is performed by bit 1 (data bus buffer function selection bit) of the data bus buffer control register (address 002a 16 ). port p4 7 be- comes s 1 input in the double data bus buffer mode. when data is written from the host cpu side, an input buffer full interrupt oc- curs. when data is read from the host cpu, an output buffer empty interrupt occurs. this microcomputer shares two input buffer full interrupt requests and two output buffer empty interrupt requests as shown in figure 34, respectively. fig. 34 interrupt request circuit of data bus buffer functional description input buffer full flag 0 ibf 0 i n p u t b u f f e r f u l l f l a g 1 i b f 1 r i s i n g e d g e d e t e c t i o n c i r c u i t one-shot pulse generating circuit o n e - s h o t p u l s e g e n e r a t i n g c i r c u i t input buffer full interrupt request signal ibf o u t p u t b u f f e r f u l l f l a g 0 o b f 0 o u t p u t b u f f e r f u l l f l a g 1 o b f 1 o n e - s h o t p u l s e g e n e r a t i n g c i r c u i t o n e - s h o t p u l s e g e n e r a t i n g c i r c u i t output buffer empty interrupt request signal obe interrupt request is set at this rising edge i n t e r r u p t r e q u e s t i s s e t a t t h i s r i s i n g e d g e i b f 0 i b f 1 i b f obf 0 ( obe 0) o b f 1 ( o b e 1 ) o b e o b e 0 o b e 1 r i s i n g e d g e d e t e c t i o n c i r c u i t r i s i n g e d g e d e t e c t i o n c i r c u i t r i s i n g e d g e d e t e c t i o n c i r c u i t
3886 group user s manual fig. 35 structure of bus interface related register functional description data bus buffer control register b 0 b 7 d a t a b u s b u f f e r e n a b l e b i t 0 : p 5 0 p 5 3 , p 8 i / o p o r t 1 : d a t a b u s b u f f e r e n a b l e d d a t a b u s b u f f e r f u n c t i o n s e l e c t i o n b i t 0 : s i n g l e d a t a b u s b u f f e r m o d e ( p 4 7 f u n c t i o n s a s i / o p o r t . ) 1 : d o u b l e d a t a b u s b u f f e r m o d e ( p 4 7 f u n c t i o n s s 1 i n p u t . ) o b f 0 o u t p u t s e l e c t i o n b i t 0 : o b f 0 0 v a l i d 1 : o b f 0 1 v a l i d o b f 0 0 o u t p u t e n a b l e b i t 0 : p 4 2 f u n c t i o n s a s p o r t i / o p i n . 1 : p 4 2 f u n c t i o n s a s o b f 0 0 o u t p u t p i n . o b f 0 1 o u t p u t e n a b l e b i t 0 : p 4 3 f u n c t i o n s a s p o r t i / o p i n . 1 : p 4 3 f u n c t i o n s a s o b f 0 1 o u t p u t p i n . o b f 1 0 o u t p u t e n a b l e b i t 0 : p 4 6 f u n c t i o n s a s p o r t i / o p i n . 1 : p 4 6 f u n c t i o n s a s o b f 1 0 o u t p u t p i n . i n p u t l e v e l s e l e c t i o n b i t 0 : c m o s l e v e l i n p u t 1 : t t l l e v e l i n p u t r e s e r v e d d o n o t w r i t e 1 t o t h i s b i t . d a t a b u s b u f f e r s t a t u s r e g i s t e r 1 output buffer full flag 1 (obf 1 ) i n p u t b u f f e r f u l l f l a g 1 ( i b f 1 ) u s e r d e f i n a b l e f l a g ( u 1 2 ) a 0 1 f l a g ( a 0 1 ) u s e r d e f i n a b l e f l a g ( u 1 4 u 1 7 ) t h i s f l a g c a n b e d e f i n e d b y u s e r f r e e l y . this flag can be defined by user freely. t h i s f l a g i n d i c a t e s t h e c o n d i t i o n o f a 0 1 s t a t u s w h e n t h e i b f 1 f l a g i s s e t . 0 : b u f f e r e m p t y 1 : buffer full 0 : b u f f e r e m p t y 1 : buffer full d a t a b u s b u f f e r s t a t u s r e g i s t e r 0 output buffer full flag 0 (obf 0 ) input buffer full flag 0 (ibf 0 ) u s e r d e f i n a b l e f l a g ( u 0 2 ) a 0 0 f l a g ( a 0 0 ) this flag can be defined by user freely. this flag can be defined by user freely. t h i s f l a g i n d i c a t e s t h e c o n d i t i o n o f a 0 0 s t a t u s w h e n t h e i b f 0 f l a g i s s e t . 0 : b u f f e r e m p t y 1 : b u f f e r f u l l 0 : b u f f e r e m p t y 1 : buffer full b 0 b 7 b0 b 7 ( d b b c o n : a d d r e s s 0 0 2 a 1 6 ) ( d b b s t s 0 : a d d r e s s 0 0 2 9 1 6 ) u s e r d e f i n a b l e f l a g ( u 0 4 u 0 7 ) ( d b b s t s 1 : a d d r e s s 0 0 2 c 1 6 )
3886 group user s manual hardware fig. 36 bus interface device block diagram functional description p8 0 /dq 0 rd wr d b b 0 dbbsts 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 u 17 u 1 6 u 1 5 u 1 4 a 0 1 u 1 2 ibf 1 obf 1 u 0 7 u 06 u 0 5 u 0 4 a 0 0 u 0 2 ibf 0 o b f 0 p8 1 /dq 1 p8 2 /dq 2 p8 3 /dq 3 p8 4 /dq 4 p8 5 /dq 5 p8 6 /dq 6 p8 7 /dq 7 p5 1 /int 20 /s 0 p 5 2 / i n t 3 0 / r p 5 3 / i n t 4 0 / w p 4 7 / s r d y 1 / s 1 ( a d d r e s s 0 0 2 a 1 6 ) rd d b b s t s 0 d b b 1 wr p 4 3 / i n t 1 / o b f 0 1 p 4 2 / i n t 0 / o b f 0 0 p 4 6 / s c l k 1 / o b f 1 0 (address 002c 16 ) (address 0029 16 ) input data bus buffer 0 output data bus buffer 0 output data bus buffer 1 i n t e r n a l d a t a b u s s y s t e m b u s input data bus buffer 1 p 5 0 / a 0 (address 0028 16 ) (address 0028 16 ) (address 002b 16 ) (address 002b 16 )
3886 group user s manual [data bus buffer status register 0, 1 (dbbsts0, dbbsts1)] 0029 16 , 002c 16 the data bus buffer status registers 0 and 1 consist of eight bits. bits 0, 1, and 3 are read-only bits and indicate the condition of the data bus buffer. bits 2, 4, 5, 6, and 7 are user definable flags which can be set by program, and can be read/written. this regis- ter can be read from the host cpu when the a 0 pin is set to h only. ?it 0: output buffer full flag obf 0 , obf 1 when writing data to the output data bus buffer, these flags are set to 1 . when reading the output data bus buffer from the host cpu, these flags are cleared to 0 . ?it 1: input buffer full flag ibf 0 , ibf 1 when writing data from the host cpu to the input data bus buffer, these flags are set to 1 . when reading the input data bus buffer from the slave cpu side, these flags are cleared to 0 . ?it 3: a 0 flag a0 0 , a0 1 when writing data from the host cpu to the input data bus buffer, the level of the a 0 pin is latched. [input data bus buffer register 0, 1 (dbbin0, dbbin1)] 0028 16 , 002b 16 data on the data bus is latched to dbbin by writing request from the host cpu. data of dbbin can be read from the data bus buffer registers (address 0028 16 or 002b 16 ) on sfr. [output data bus buffer register 0, 1 (dbbout0, dbbout1)] 0028 16 , 002b 16 when writing data to the data bus buffer registers (address 0028 16 or 002b 16 ) on sfr, data is set to dbbout. data of dbbout is output from the host cpu to the data bus by performing the read- ing request when the a 0 pin is set to l . [port control register 2 (pctl2)] 002f 16 even if the data bus buffer function is enabled, both p4 2 and p4 3 function as ports when the obf 00 output enable bit (bit 3 of ad- dress 2a 16 ) or the obf 01 output enable bit (bit 4 of address 2a 16 ) is 0 . ports p4 2 and p4 3 are cleared to 0 by changing the input buffer full flag 0 (bit 1 of address 29 16 ) from 1 to 0 under the fol- lowing conditions: the port output p4 2 /p4 3 clear function selection bit (bit 7) is set to 1 , both ports are in the output mode of the port function, and both port latches are 1 . functional description
3886 group user s manual hardware p4 7 /srdy 1 /s 1 p5 0 /a 0 p5 1 /int 20 /s 0 p5 2 /int 30 /r p5 3 /int 40 /w p4 2 /int 0 /obf 00 p4 3 /int 1 /obf 01 p4 6 /s clk1 /obf 10 table 10 function description of control i/o pins at bus interface function selected pin name obf 00 output enable bit obf 01 output enable bit obf 10 output enable bit input /output functions s 1 a 0 s 0 r w obf 00 obf 01 obf 10 chip select input this is used for selecting the data bus buffer 1 and is selected at l level. address input this is used for selecting dbbsts and dbbout when the host cpu is read. this is used for distinguishing command from data when writing to the host cpu. chip select input this is used for selecting the data bus buffer 0 and is selected at l level. this is a timing signal for reading data from the data bus buffer to the host cpu. this is a timing signal for writing data to the data bus buffer by the host cpu. status output signal obf 00 signal is output. status output signal obf 01 signal is output. status output signal obf 10 signal is output. 1 0 0 0 1 0 0 0 1 input input input input input output output output functional description
3886 group user s manual function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at = 4 mhz) 20.2 khz to 312.5 khz (at = 5 mhz) table 11 multi-master i 2 c-bus interface functions item format communication mode s cl clock frequency system clock = f(x in )/2 (high-speed mode) = f(x in )/8 (middle-speed mode) multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchro- nous functions, is useful for the multi-master serial communications. figure 37 shows a block diagram of the multi-master i 2 c-bus in- terface and table 11 lists the multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c address register, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register, the i 2 c start/stop condition control register and other control circuits. when using the multi-master i 2 c-bus interface, set 1 mhz or more to . fig. 37 block diagram of multi-master i 2 c-bus interface ? : purchase of mitsubishi electric corporations i 2 c components conveys a license under the philips i 2 c patent rights to use these components an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. functional description i 2 c a d d r e s s r e g i s t e r b7 b 0 s a d 6s a d 5sad 4 s a d 3s a d 2s a d 1sad0 r w b noise elimination circuit serial data (s d a ) a d d r e s s c o m p a r a t o r b7 i 2 c data shift register b0 data control circuit system clock (
3886 group user s manual hardware [i 2 c data shift register (s0)] 0012 16 the i 2 c data shift register (s0 : address 0012 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the s cl clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the s cl clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. the minimum 2 cycles of are required from the rising of the s cl clock until input to this register. the i 2 c data shift register is in a write enable status only when the i 2 c-bus interface enable bit (es0 bit : bit 3 of address 15 16 ) of the i 2 c control register is 1. the bit counter is reset by a write in- struction to the i 2 c data shift register. when both the es0 bit and the mst bit of the i 2 c status register (address 0014 16 ) are 1, the s cl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift register is always enabled re- gardless of the es0 bit value. [i 2 c address register (s0d)] 0013 16 the i 2 c address register (address 0013 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition is detected. ?it 0: read/write bit (rwb) this is not used in the 7-bit addressing mode. in the 10-bit ad- dressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rwb) of the i 2 c address reg- ister. the rwb bit is cleared to 0 automatically when the stop condi- tion is detected. ?its 1 to 7: slave address (sad0?ad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. fig. 38 structure of i 2 c address register functional description sad6 s a d 5 sad4 s a d 3 sad2 s a d 1s a d 0r w b s l a v e a d d r e s s i 2 c address register (s0d: address 0013 16 ) r e a d / w r i t e b i t b 7b0
3886 group user s manual table 12 set values of i 2 c clock control register and s cl frequency fig. 39 structure of i 2 c clock control register s cl frequency (at = 4 mhz, unit : khz) (note 1) setting value of ccr4 ccr0 standard clock mode setting disabled setting disabled setting disabled high-speed clock mode ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 notes 1: duty of s cl clock output is 50 %. the duty becomes 35 to 45 % only when the high-speed clock mode is selected and ccr value = 5 (400 khz, at = 4 mhz). h duration of the clock fluctuates from 4 to +2 cycles of in the standard clock mode, and fluctu- ates from 2 to +2 cycles of in the high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because l duration is extended instead of h duration reduc- tion. these are value when s cl clock synchronization by the synchro- nous function is not performed. ccr value is the decimal notation value of the s cl frequency control bits ccr4 to ccr0. 2: each value of s cl frequency exceeds the limit at = 4 mhz or more. when using these setting value, use of 4 mhz or less. 3: the data formula of s cl frequency is described below: /(8 ? ccr value) standard clock mode /(4 ? ccr value) high-speed clock mode (ccr value 5) /(2 ? ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as ccr value regardless of frequency. set 100 khz (max.) in the standard clock mode and 400 khz (max.) in the high-speed clock mode to the s cl frequency by set- ting the s cl frequency control bits ccr4 to ccr0. setting disabled setting disabled setting disabled 1000/ccr value (note 3) 34.5 33.3 32.3 500/ccr value (note 3) 17.2 16.6 16.1 333 250 400 (note 3) 166 (note 2) (note 2) 100 83.3 [i 2 c clock control register (s2)] 0016 16 the i 2 c clock control register (address 0016 16 ) is used to set ack control, s cl mode and s cl frequency. ?its 0 to 4: s cl frequency control bits (ccr0?cr4) these bits control the s cl frequency. refer to table 12. ?it 5: s cl mode specification bit (fast mode) this bit specifies the s cl mode. when this bit is set to 0, the standard clock mode is selected. when the bit is set to 1, the high-speed clock mode is selected. when connecting the bus according to the high-speed mode i 2 c bus standard (maximum 400 kbits/s), use 8 mhz or more oscilla- tion frequency f(x in ) and high-speed mode (2 division main clock). ?it 6: ack bit (ack bit) this bit sets the s da status when an ack clock ? is generated. when this bit is set to 0, the ack return mode is selected and s da goes to l at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is selected. the s da is held in the h status at the occurrence of an ack clock. however, when the slave address agree with the address data in the reception of address data at ack bit = 0, the s da is auto- matically made l (ack is returned). if there is a disagreement between the slave address and the address data, the s da is auto- matically made h (ack is not returned). ? ack clock: clock for acknowledgment ?it 7: ack clock bit (ack) this bit specifies the mode of acknowledgment which is an ac- knowledgment response of data transfer. when this bit is set to 0, the no ack clock mode is selected. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is selected and the master generates an ack clock each completion of each 1-byte data transfer. the device for transmitting address data and control data releases the s da at the occurrence of an ack clock (makes s da h ) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transfer. if data is written during transfer, the i 2 c clock generator is reset, so that data cannot be transferred normally. functional description a c k a c k b i t f a s t m o d e c c r 4c c r 3 c c r 2c c r 1c c r 0 i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 : a d d r e s s 0 0 1 6 1 6 ) b 7b 0 s c l f r e q u e n c y c o n t r o l b i t s r e f e r t o t a b l e 1 2 . s c l m o d e s p e c i f i c a t i o n b i t 0 : s t a n d a r d c l o c k m o d e 1 : h i g h - s p e e d c l o c k m o d e a c k b i t 0 : a c k i s r e t u r n e d . 1 : a c k i s n o t r e t u r n e d . a c k c l o c k b i t 0 : n o a c k c l o c k 1 : a c k c l o c k
3886 group user s manual hardware fig. 40 structure of i 2 c control register [i 2 c control register (s1d)] 0015 16 the i 2 c control register (address 0015 16 ) controls data communi- cation format. ?its 0 to 2: bit counter (bc0?c2) these bits decide the number of bits for the next 1-byte data to be transmitted. the i 2 c interrupt request signal occurs immediately after the number of count specified with these bits (ack clock is added to the number of count when ack clock is selected by ack bit (bit 7 of address 0016 16 )) have been transferred, and bc0 to bc2 are returned to 000 2 . also when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. ?it 3: i 2 c interface enable bit (es0) this bit enables to use the multi-master i 2 c-bus interface. when this bit is set to 0, the use disable status is provided, so that the s da and the s cl become high-impedance. when the bit is set to 1, use of the interface is enabled. when es0 = 0, the following is performed. pin = 1, bb = 0 and al = 0 are set (which are bits of the i 2 c status register at address 0014 16 ). writing data to the i 2 c data shift register (address 0012 16 ) is dis abled. ?it 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that address data is recognized. when a match is found between a slave address and address data as a result of comparison or when a general call (refer to (5) i 2 c status register, bit 1) is re- ceived, transfer processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recognized. ?it 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address regis- ter (address 0013 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, and all the bits of the i 2 c address register are compared with address data. ?it 6: system clock stop selection bit (clkstp) when executing the wit or stp instruction, this bit selects the condition of system clock provided to the multi-master i 2 c-bus in- terface. when this bit is set to 0, system clock and operation of the multi-master i 2 c-bus interface stop by executing the wit or stp instruction. when this bit is set to 1, system clock and operation of the multi- master i 2 c-bus interface do not stop even when the wit instruction is executed. when the system clock stop selection bit is 1, do not execute the stp instruction. ?it 7: i 2 c-bus interface pin input level selection bit this bit selects the input level of the s cl and s da pins of the multi- master i 2 c-bus interface. functional description b7 tiss c l k s t p 1 0 b i t s a d als e s 0 bc 2 bc 1 bc 0 b0 system clock stop selection bit 0 : system clock stop when executing wit or stp instruction 1 : not system clock stop when executing wit instruction (do not use the stp instruction.) i 2 c c o n t r o l r e g i s t e r ( s 1 d : a d d r e s s 0 0 1 5 1 6 ) b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c e i v e b i t s ) b 2b 1b 0 00 0: 8 00 1: 7 01 0: 6 01 1: 5 10 0: 4 10 1: 3 11 0: 2 11 1: 1 i 2 c - b u s i n t e r f a c e e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d d a t a f o r m a t s e l e c t i o n b i t 0 : a d d r e s s i n g f o r m a t 1 : f r e e d a t a f o r m a t a d d r e s s i n g f o r m a t s e l e c t i o n b i t 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t i 2 c-bus interface pin input level selection bit 0 : cmos input 1 : smbus input
3886 group user s manual ?it 4: s cl pin low hold bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the pin bit changes from 1 to 0. at the same time, an interrupt request signal occurs to the cpu. the pin bit is set to 0 in synchronization with a falling of the last clock (in- cluding the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the pin bit. when the pin bit is 0, the s cl is kept in the 0 state and clock generation is disabled. figure 42 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in one of the following conditions: executing a write instruction to the i 2 c data shift register (ad- dress 0012 16 ). (this is the only condition which the prohibition of the internal clock is released and data can be communicated ex- cept for the start condition detection.) when the es0 bit is 0 at reset when writing 1 to the pin bit by software the conditions in which the pin bit is set to 0 are shown below: immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) immediately after completion of 1-byte data reception in the slave reception mode, with als = 0 and immediately af- ter completion of slave address agreement or general call address reception in the slave reception mode, with als = 1 and immediately af- ter completion of address data reception ?it 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. the bb flag is set/reset by the s cl , s da pins in- put signal regardless of master/slave. this flag is set to 1 by detecting the start condition, and is set to 0 by detecting the stop condition. the condition of these detecting is set by the start/stop condition setting bits (ssc4 ssc0) of the i 2 c start/stop condition control register (address 0017 16 ). when the es0 bit (bit 3) of the i 2 c control register (address 0015 16 ) is 0 or reset, the bb flag is set to 0. for the writing function to the bb flag, refer to the sections start condition generating method and stop condition gen- erating method described later. [i 2 c status register (s1)] 0014 16 the i 2 c status register (address 0014 16 ) controls the i 2 c-bus in- terface status. the low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. set 0000 2 to the low-order 4 bits, because these bits become the reserved bits at writing. ?it 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 0012 16 ). ?it 1: general call detecting flag (ad0) when the als bit is 0, this bit is set to 1 when a general call ? whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives con- trol data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition, or reset. ? general call: the master transmits the general call address 00 16 to all slaves. ?it 2: slave address comparison flag (aas) this flag indicates a comparison result of address data when the als bit is 0 . ? in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions: the address data immediately after occurrence of a start condition agrees with the slave address stored in the high-or- der 7 bits of the i 2 c address register (address 0013 16 ). a general call is received. ? in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition: when the address data is compared with the i 2 c address reg- ister (8 bits consisting of slave address and rwb bit), the first bytes agree. ? this bit is set to 0 by executing a write instruction to the i 2 c data shift register (address 0012 16 ) when es0 is set to 1 or reset. ?it 3: arbitration lost ? detecting flag (al) in the master transmission mode, when the sda is made l by any other device, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediately after transmission of the byte whose arbitration was lost is completed, the mst bit is set to 0. the arbitration lost can be detected only in the master transmission mode. when ar- bitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to detect the agreement of its own slave address and ad- dress data transmitted by another master device. ? arbitration lost : the status in which communication as a master is dis- abled. functional description
3886 group user s manual hardware fig. 42 interrupt request signal generating timing fig. 41 structure of i 2 c status register ?it 6: communication mode specification bit (transfer direc- tion specification bit: trx) this bit decides a direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a transmitting device is received. when the bit is 1, the transmis- sion mode is selected and address data and control data are output onto the s da in synchronization with the clock generated on the s cl . this bit is set/reset by software and hardware. about set/reset by hardware is described below. this bit is set to 1 by hardware when all the following conditions are satisfied: when als is 0 in the slave reception mode or the slave transmission mode when the r/w bit reception is 1 this bit is set to 0 in one of the following conditions: when arbitration lost is detected. when a stop condition is detected. when writing 1 to this bit by software is invalid by the start condition duplication preventing function (note) . with mst = 0 and when a start condition is detected. with mst = 0 and when ack non-return is detected. at reset ?it 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are generated. additionally, the clocks required for data communi- cation are generated on the scl. this bit is set to 0 in one of the following conditions. immediately after completion of 1-byte data transfer when arbi- tration lost is detected when a stop condition is detected. writing 1 to this bit by software is invalid by the start condi- tion duplication preventing function (note) . at reset note: start condition duplication preventing function the mst, trx, and bb bits is set to 1 at the same time after con- firming that the bb flag is 0 in the procedure of a start condition occurrence. however, when a start condition by another master device occurs and the bb flag is set to 1 immediately after the con- tents of the bb flag is confirmed, the start condition duplication preventing function makes the writing to the mst and trx bits in- valid. the duplication preventing function becomes valid from the rising of the bb flag to reception completion of slave address. functional description b 7 m s t b 0 i 2 c s t a t u s r e g i s t e r ( s 1 : a d d r e s s 0 0 1 4 1 6 ) l a s t r e c e i v e b i t ( n o t e ) 0 :l a s t b i t = 0 1 :l a s t b i t = 1 g e n e r a l c a l l d e t e c t i n g f l a g ( n o t e ) 0 :n o g e n e r a l c a l l d e t e c t e d 1 :g e n e r a l c a l l d e t e c t e d s l a v e a d d r e s s c o m p a r i s o n f l a g ( n o t e ) 0 : a d d r e s s d i s a g r e e m e n t 1 : a d d r e s s a g r e e m e n t a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( n o t e ) 0 :n o t d e t e c t e d 1 :d e t e c t e d s c l p i n l o w h o l d b i t 0 : l o w h o l d 1 : o p e n b u s b u s y f l a g 0 : b u s f r e e 1 : b u s b u s y c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s 0 0 :s l a v e r e c e i v e m o d e 0 1 :s l a v e t r a n s m i t m o d e 1 0 :m a s t e r r e c e i v e m o d e 1 1 :m a s t e r t r a n s m i t m o d e t r xb bp i na la a sa d 0l r b n o t e : t h e s e b i t a n d f l a g s c a n b e r e a d o u t b u t c a n n o t b e w r i t t e n . w r i t e 0 t o t h e s e b i t s a t w r i t i n g . s c l pin i 2 c i r q
3886 group user s manual + 2 cycles (3.375 s) + 1 cycle < 4.0 s (3.25 s) fig. 45 start condition detecting timing diagram start/stop condition detecting operation the start/stop condition detection operations are shown in figures 45, 46, and table 15. the start/stop condition is set by the start/stop condition set bit. the start/stop condition can be detected only when the input signal of the s cl and s da pins satisfy three conditions: s cl re- lease time, setup time, and hold time (see table 15). the bb flag is set to 1 by detecting the start condition and is reset to 0 by detecting the stop condition. the bb flag set/reset timing is different in the standard clock mode and the high-speed clock mode. refer to table 15, the bb flag set/ reset time. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal i 2 cirq occurs to the cpu. table 15 start condition/stop condition detecting conditions note: unit : cycle number of system clock ssc value is the decimal notation value of the start/stop condi- tion set bits ssc4 to ssc0. do not set 0 or an odd number to ssc value. the value in parentheses is an example when the i 2 c start/ stop condition control register is set to 18 16 at = 4 mhz. fig. 46 stop condition detecting timing diagram s cl release time standard clock mode high-speed clock mode 4 cycles (1.0 s) 2 cycles (1.0 s) 2 cycles (0.5 s) 3.5 cycles (0.875 s) ssc value 2 ssc value 2 ssc value 1 2 setup time hold time bb flag set/ reset time ssc value + 1 cycle (6.25 s) cycle < 4.0 s (3.0 s) start condition generating method when writing 1 to the mst, trx, and bb bits of the i 2 c status register (address 0014 16 ) at the same time after writing the slave address to the i 2 c data shift register (address 0012 16 ) with the condition in which the es0 bit of the i 2 c control register (address 0015 16 ) and the bb flag are 0 , a start condition occurs. after that, the bit counter becomes 000 2 and an s cl for 1 byte is out- put. the start condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 43, the start condition generating timing diagram, and table 13, the start condition generating timing table. stop condition generating method when the es0 bit of the i 2 c control register (address 0015 16 ) is 1, write 1 to the mst and trx bits, and write 0 to the bb bit of the i 2 c status register (address 0014 16 ) simultaneously. then a stop condition occurs. the stop condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 44, the stop condition generating timing diagram, and table 14, the stop condition generating timing table. fig. 43 start condition generating timing diagram fig. 44 stop condition generating timing diagram table 14 stop condition generating timing table item setup time start/stop condition generating selection bit 0 1 0 1 standard clock mode 5.5 s (22 cycles) 13.5 s (54 cycles) 5.5 s (22 cycles) 13.5 s (54 cycles) note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. high-speed clock mode 3.0 s (12 cycles) 7.0 s (28 cycles) 3.0 s (12 cycles) 7.0 s (28 cycles) table 13 start condition generating timing table item setup time start/stop condition generating selection bit standard clock mode note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. high-speed clock mode 0 1 0 1 5.0 s (20 cycles) 13.0 s (52 cycles) 5.0 s (20 cycles) 13.0 s (52 cycles) 2.5 s (10 cycles) 6.5 s (26 cycles) 2.5 s (10 cycles) 6.5 s (26 cycles) hold time hold time functional description i 2 c s t a t u s r e g i s t e r w r i t e s i g n a l h o l d t i m e setup time s c l s da i 2 c status register write signal hold time s e t u p t i m e s cl s da h o l d t i m e setup time s c l s da b b f l a g s cl release time bb flag reset time h o l d t i m e setup time s c l s da b b f l a g s cl release time b b f l a g r e s e t t i m e
3886 group user s manual hardware [i 2 c start/stop condition control register (s2d)] 0017 16 the i 2 c start/stop condition control register (address 0017 16 ) controls start/stop condition detection. bits 0 to 4: start/stop condition set bit (ssc4 ssc0) s cl release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(x in ) because these time are measured by the internal system clock. accordingly, set the proper value to the start/stop condition set bits (ssc4 to ssc0) in considered of the system clock frequency. refer to table 16. do not set 00000 2 or an odd number to the start/stop condi- tion set bit (ssc4 to ssc0). bit 5: s cl /s da interrupt pin polarity selection bit (sip) an interrupt can occur when detecting the falling or rising edge of the s cl or s da pin. this bit selects the polarity of the s cl or s da pin interrupt pin. bit 6: s cl /s da interrupt pin selection bit (sis) this bit selects the pin of which interrupt becomes valid between the s cl pin and the s da pin. note: when changing the setting of the s cl /s da interrupt pin polarity se- lection bit, the s cl /s da interrupt pin selection bit, or the i 2 c-bus interface enable bit es0, the s cl /s da interrupt request bit may be set. when selecting the s cl /s da interrupt source, disable the inter- rupt before the s cl /s da interrupt pin polarity selection bit, the s cl / s da interrupt pin selection bit, or the i 2 c-bus interface enable bit es0 is set. reset the request bit to 0 after setting these bits, and enable the interrupt. bit 7: start/stop condition generating selection bit (stspsel) setup/hold time when the start/stop condition is generated can be selected. cycle number of system clock becomes standard for setup/hold time. additionally, setup/hold time is different between the start condition and the stp condition. (refer to tables 13 and 14.) set 1 to this bit when the system clock frequency is 4 mhz or more. address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective address communication formats are described below. ? 7-bit addressing format to adapt the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 0015 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 0013 16 ). at the time of this comparison, address com- parison of the rwb bit of the i 2 c address register (address 0013 16 ) is not performed. for the data transmission format when the 7-bit addressing format is selected, refer to figure 48, (1) and (2). ? 10-bit addressing format to adapt the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 0015 16 ) to 1. an address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the i 2 c address register (address 0013 16 ). at the time of this comparison, an address comparison between the rwb bit of the i 2 c address register (address 0013 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the rwb bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is pro- cessed as an address data bit. when the first-byte address data agree with the slave address, the aas bit of the i 2 c status register (address 0014 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 0012 16 ), perform an address com- parison between the second-byte data and the slave address by software. when the address data of the 2 bytes agree with the slave address, set the rwb bit of the i 2 c address register (address 0013 16 ) to 1 by software. this processing can make the 7-bit slave address and r/w data agree, which are re- ceived after a restart condition is detected, with the value of the i 2 c address register (address 0013 16 ). for the data trans- mission format when the 10-bit addressing format is selected, refer to figure 48, (3) and (4). functional description
3886 group user s manual start/stop condition control register oscillation frequency f(x in ) (mhz) fig. 48 address data communication format fig. 47 structure of i 2 c start/stop condition control register note: do not set 00000 2 or an odd number to the start/stop condition set bit (ssc4 to ssc0). table 16 recommended set value to start/stop condition set bits (ssc4 ssc0) for each oscillation frequency main clock divide ratio system clock (mhz) s cl release time ( s) setup time ( s) hold time ( s) 10 8 8 4 2 2 2 8 2 2 xxx11110 xxx11010 xxx11000 xxx00100 xxx01100 xxx01010 xxx00100 3.2 s (16 cycles) 3.5 s (14 cycles) 3.25 s (13 cycles) 3.0 s (3 cycles) 3.5 s (7 cycles) 3.0 s (6 cycles) 3.0 s (3 cycles) 6.2 s (31 cycles) 6.75 s (27 cycles) 6.25 s (25 cycles) 5.0 s (5 cycles) 6.5 s (13 cycles) 5.5 s (11 cycles) 5.0 s (5 cycles) 3.0 s (15 cycles) 3.25 s (13 cycles) 3.0 s (12 cycles) 2.0 s (2 cycles) 3.0 s (6 cycles) 2.5 s (5 cycles) 2.0 s (2 cycles) 5 4 1 2 1 functional description b 7 s t s p s e l b 0 i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r s t a r t / s t o p c o n d i t i o n s e t b i t s c l / s d a i n t e r r u p t p i n p o l a r i t y s e l e c t i o n b i t 0 :f a l l i n g e d g e a c t i v e 1 :r i s i n g e d g e a c t i v e s c l / s d a i n t e r r u p t p i n s e l e c t i o n b i t 0 :s d a v a l i d 1 :s c l v a l i d s t a r t / s t o p c o n d i t i o n g e n e r a t i n g s e l e c t i o n b i t 0 :s e t u p / h o l d t i m e s h o r t m o d e 1 :s e t u p / h o l d t i m e l o n g m o d e s i s s i p s s c 4s s c 3s s c 2s s c 1s s c 0 ( s 2 d : a d d r e s s 0 0 1 7 1 6 ) ss l a v e a d d r e s sr / w ad a t aa data a / a p 7 b i t s 0 1 t o 8 b i t s1 t o 8 b i t s ( 1 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r s s l a v e a d d r e s s r / w ad a t aadata a p 7 bits 1 1 to 8 bits 1 to 8 bits ( 2 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r s s l a v e a d d r e s s 1 s t 7 b i t s r / w a 7 b i t s 0 8 b i t s ( 3 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r w i t h a 1 0 - b i t a d d r e s s s l a v e a d d r e s s 2 n d b y t e s a d a t a ad a t a a / a p 1 t o 8 b i t s1 t o 8 b i t s s s l a v e a d d r e s s 1 s t 7 b i t s r / w a 7 b i t s 0 8 b i t s ( 4 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r w i t h a 1 0 - b i t a d d r e s s s l a v e a d d r e s s 2 n d b y t e s adata a a s r s l a v e a d d r e s s 1 s t 7 b i t s r / w a data p s : s t a r t c o n d i t i o n a : a c k b i t s r : r e s t a r t c o n d i t i o n p : s t o p c o n d i t i o n r / w : r e a d / w r i t e b i t 7 b i t s 1 1 to 8 bits 1 to 8 bits
3886 group user s manual hardware example of master transmission an example of master transmission in the standard clock mode, at the s cl frequency of 100 khz and in the ack return mode is shown below. ? set a slave address in the high-order 7 bits of the i 2 c address register (address 0013 16 ) and 0 into the rwb bit. ? set the ack return mode and s cl = 100 khz by setting 85 16 in the i 2 c clock control register (address 0016 16 ). ? set 00 16 in the i 2 c status register (address 0014 16 ) so that transmission/reception mode can become initializing condition. ? set a communication enable status by setting 08 16 in the i 2 c control register (address 0015 16 ). ? confirm the bus free condition by the bb flag of the i 2 c status register (address 0014 16 ). ? set the address data of the destination of transmission in the high-order 7 bits of the i 2 c data shift register (address 0012 16 ) and set 0 in the least significant bit. ? set f0 16 in the i 2 c status register (address 0014 16 ) to gener- ate a start condition. at this time, an s cl for 1 byte and an ack clock automatically occur. ? set transmit data in the i 2 c data shift register (address 0012 16 ). at this time, an s cl and an ack clock automatically occur. ? when transmitting control data of more than 1 byte, repeat step ? . ? set d0 16 in the i 2 c status register (address 0014 16 ) to gener- ate a stop condition if ack is not returned from slave reception side or transmission ends. example of slave reception an example of slave reception in the high-speed clock mode, at the s cl frequency of 400 khz, in the ack non-return mode and using the addressing format is shown below. ? set a slave address in the high-order 7 bits of the i 2 c address register (address 0013 16 ) and 0 in the rwb bit. ? set the no ack clock mode and s cl = 400 khz by setting 25 16 in the i 2 c clock control register (address 0016 16 ). ? set 00 16 in the i 2 c status register (address 0014 16 ) so that transmission/reception mode can become initializing condition. ? set a communication enable status by setting 08 16 in the i 2 c control register (address 0015 16 ). ? when a start condition is received, an address comparison is performed. ? when all transmitted addresses are 0 (general call): ad0 of the i 2 c status register (address 0014 16 ) is set to 1 and an interrupt request signal occurs. when the transmitted addresses agree with the address set in ? : aas of the i 2 c status register (address 0014 16 ) is set to 1 and an interrupt request signal occurs. in the cases other than the above ad0 and aas of the i 2 c sta- tus register (address 0014 16 ) are set to 0 and no interrupt request signal occurs. ? set dummy data in the i 2 c data shift register (address 0012 16 ). ? when receiving control data of more than 1 byte, repeat step ? . ? when a stop condition is detected, the communication ends. (1) read-modify-write instruction the precautions when the read-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. i 2 c data shift register (s0: address 0012 16 ) when executing the read-modify-write instruction for this regis- ter during transfer, data may become a value not intended. i 2 c address register (s0d: address 0013 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the stop condition, data may become a value not intended. it is because h/w changes the read/write bit (rwb) at the above timing. i 2 c status register (s1: address 0014 16 ) do not execute the read-modify-write instruction for this register because all bits of this register are changed by h/w. i 2 c control register (s1d: address 0015 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the start condition or at completing the byte transfer, data may become a value not intended. because h/w changes the bit counter (bc0-bc2) at the above timing. i 2 c clock control register (s2: address 0016 16 ) the read-modify-write instruction can be executed for this regis- ter. i 2 c start/stop condition control register (s2d: address 0017 16 ) the read-modify-write instruction can be executed for this regis- ter. functional description
3886 group user s manual ..... ..... ..... ..... ..... (2) start condition generating procedure using multi-master 1. procedure example (the necessary conditions of the generat- ing procedure are described in items 2 to 5 below. lda (taking out of slave address value) sei (interrupt disabled) bbs 5, s1, busbusy (bb flag confirming and branch process) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) busbusy: cli (interrupt enabled) 2. use branch on bit set of bbs 5, $0014, for the bb flag confirming and branch process. 3. use sta $12, stx $12 or sty $12 of the zero page ad- dressing instruction for writing the slave address value to the i 2 c data shift register. 4. execute the branch instruction of item 2 and the store instruc- tion of item 3 continuously, as shown in the procedure example above. 5. disable interrupts during the following three process steps: bb flag confirming writing of slave address value trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. (3) restart condition generating procedure this procedure cannot be applied to m3886 7m8a and m3886 7e8a when the external memory is used and the bus cycle is extended by onw function. 1. procedure example (the necessary conditions for the proce- dure are described in items 2 to 4 below.) execute the following procedure when the pin bit is 0. ldm #$00, s1 (select slave receive mode) lda (take out of slave address value) sei (disable interrupt) sta s0 (write slave address value) ldm #$f0, s1 ( trigger restart condition generation ) cli (enable interrupt) 2. select the slave receive mode when the pin bit is 0. do not write 1 to the pin bit. neither 0 nor 1 is specified as input to the bb bit. the trx bit becomes 0 and the s da pin is released. 3. the s cl pin is released by writing the slave address value to the i 2 c data shift register. 4. disable interrupts during the following two process steps: write slave address value trigger restart condition generation (4) writing to i 2 c status register do not execute an instruction to set the pin bit to 1 from 0 and an instruction to set the mst and trx bits to 0 from 1 simulta- neously. because it may enter the state that the s cl pin is released and the s da pin is released after about one machine cycle. do not execute an instruction to set the mst and trx bits to 0 from 1 simultaneously when the pin bit is 1. because it may become the same as above. (5) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c sta- tus register s1 until the bus busy flag bb becomes 0 after generating the stop condition in the master mode. because the stop condition waveform might not be normally generated. reading to the above registers do not have the problem. (6) stop condition input at 7th clock pulse the sda line may be held at low even if flag bb is set to 0 when all the following conditions are satisfied: in the slave mode the stop condition is input at the 7th clock pulse while receiving a slave address or data. the clock pulse is continuously input. countermeasure: write dummy data to the i 2 c shift register or reset the es0 bit in the s1d register (es0 = l es0 = h ) during a stop condition interrupt routine with flag pin = 1 . note: do not use the read-modify-write instruction at this time. furthermore, when the es0 bit is set to 0 , the sda pin be- comes a general-purpose port; the port must be set to input mode or output h . (7) es0 bit switch in standard clock mode when ssc = 00010 2 or in high-speed clock mode, flag bb may switch to 1 if es0 bit is set to 1 when sda is l . countermeasure: set es0 to 1 when sda is h . functional description
3886 group user? manual hardware a-d converter [a-d conversion register 1,2 (ad1, ad2)] 0035 16 , 0038 16 the a-d conversion register is a read-only register that stores the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. bit 7 of the a-d conversion register 2 is the conversion mode se- lection bit. when this bit is set to ?,?the a-d converter becomes the 10-bit a-d mode. when this bit is set to ?,?that becomes the 8-bit a-d mode. the conversion result of the 8-bit a-d mode is stored in the a-d conversion register 1. as for 10-bit a-d mode, 10-bit reading or 8-bit reading can be performed by selecting the reading procedure of the a-d conversion register 1, 2 after a-d conversion is completed (in figure 50). the a-d conversion register 1 performs the 8-bit reading inclined to msb after reset, the a-d conversion is started, or reading of the a-d converter register 1 is generated; and the register becomes the 8-bit reading inclined to lsb after the a-d converter register 2 is generated. [ad/da control register (adcon)] 0034 16 the ad/da control register controls the a-d conversion process. bits 0 to 2 select a specific analog input pin. bit 3 signals the completion of an a-d conversion. the value of this bit remains at ??during an a-d conversion, and changes to ??when an a-d conversion ends. writing ??to this bit starts the a-d conversion. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref into 1024, and outputs the divided voltages in the 10-bit a-d mode (256 division in 8-bit a-d mode). the a-d converter successively compares the comparison voltage v ref in each mode, dividing the v ref (see below), with the input voltage. 10-bit a-d mode (10-bit reading) v ref = ? n (n = 0?023) 10-bit a-d mode (8-bit reading) v ref = ? n (n = 0?55) 8-bit a-d mode v ref = ? (n?.5) (n = 1?55) =0 (n = 0) fig. 49 structure of ad/da control register channel selector the channel selector selects one of ports p6 0 /an 0 to p6 7 /an 7 , and inputs the voltage to the comparator. comparator and control circuit the comparator and control circuit compares an analog input volt- age with the comparison voltage, and then stores the result in the a-d conversion registers 1, 2. when an a-d conversion is com- pleted, the control circuit sets the a-d conversion completion bit and the a-d interrupt request bit to ?? note that because the comparator consists of a capacitor cou- pling, set f(x in ) to 500 khz or more during an a-d conversion. v ref 256 v ref 256 fig. 50 structure of 10-bit a-d mode reading v ref 1024 functional description a d / d a c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 4 1 6 ) a n a l o g i n p u t p i n s e l e c t i o n b i t s 0 0 0 : p 6 0 / a n 0 0 0 1 : p 6 1 / a n 1 0 1 0 : p 6 2 / a n 2 0 1 1 : p 6 3 / a n 3 1 0 0 : p 6 4 / a n 4 1 0 1 : p 6 5 / a n 5 1 1 0 : p 6 6 / a n 6 1 1 1 : p 6 7 / a n 7 a - d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d p w m 0 o u t p u t p i n s e l e c t i o n b i t 0 : p 5 6 / p w m 0 1 1 : p 3 0 / p w m 0 0 p w m 1 o u t p u t p i n s e l e c t i o n b i t 0 : p 5 7 / p w m 1 1 1 : p 3 1 / p w m 1 0 d a 1 o u t p u t e n a b l e b i t 0 : d a 1 o u t p u t d i s a b l e d 1 : d a 1 o u t p u t e n a b l e d d a 2 o u t p u t e n a b l e b i t 0 : d a 2 o u t p u t d i s a b l e d 1 : d a 2 o u t p u t e n a b l e d b 7 b 0 b 2 b 1 b 0 1 0 - b i t r e a d i n g ( r e a d a d d r e s s 0 0 3 8 1 6 b e f o r e 0 0 3 5 1 6 ) ( a d d r e s s 0 0 3 8 1 6 ) ( a d d r e s s 0 0 3 5 1 6 ) 8 - b i t r e a d i n g ( r e a d o n l y a d d r e s s 0 0 3 5 1 6 ) ( a d d r e s s 0 0 3 5 1 6 ) b 8 b 7b 6b 5b 4 b 3b 2b 1b 0 b7 b 0 b 9 b 7 b 0 n o t e : b i t s 2 t o 6 o f a d d r e s s 0 0 3 8 1 6 b e c o m e s 0 a t r e a d i n g . b 9b 8b 7b 6 b 5b 4b 3 b 2 b 7 b 0 0
3886 group user s manual fig. 51 block diagram of a-d converter functional description c h a n n e l s e l e c t o r a - d c o n t r o l c i r c u i t a-d conversion register 1 resistor ladder v ref av ss c o m p a r a t o r a - d i n t e r r u p t r e q u e s t b7 b0 3 1 0 p 6 0 / a n 0 p 6 1 / a n 1 p 6 2 / a n 2 p 6 3 / a n 3 p 6 4 / a n 4 p 6 5 / a n 5 p 6 6 / a n 6 p 6 7 / a n 7 d a t a b u s a d / d a c o n t r o l r e g i s t e r a - d c o n v e r s i o n r e g i s t e r 2 ( a d d r e s s 0 0 3 4 1 6 ) (address 0038 16 ) (address 0035 16 )
3886 group user s manual hardware d-a converter the 3886 group has two internal d-a converters (da 1 and da 2 ) with 8-bit resolution. the d-a converter is performed by setting the value in each d-a conversion register. the result of d-a conversion is output from the da 1 or da 2 pin by setting the da output enable bit to 1 . when using the d-a converter, the corresponding port direction register bit (p5 6 /da 1 /pwm 01 or p5 7 /da 2 /pwm 11 ) must be set to 0 (input status). the output analog voltage v is determined by the value n (decimal notation) in the d-a conversion register as follows: v = v ref ? n/256 (n = 0 to 255) where v ref is the reference voltage. at reset, the d-a conversion registers are cleared to 00 16 , the da output enable bits are cleared to 0 , and the p5 6 /da 1 /pwm 01 and p5 7 /da 2 /pwm 11 pins become high impedance. the da output does not have buffers. accordingly, connect an ex- ternal buffer when driving a low-impedance load. set v cc to 4.0 v or more when using the d-a converter. fig. 52 block diagram of d-a converter fig. 53 equivalent connection circuit of d-a converter (da1) functional description p 5 6 / d a 1 / p w m 0 1 d - a 1 c o n v e r s i o n r e g i s t e r ( 8 ) r - 2 r r e s i s t o r l a d d e r d a 1 o u t p u t e n a b l e b i t p 5 7 / d a 2 / p w m 1 1 d - a 2 c o n v e r s i o n r e g i s t e r ( 8 ) r - 2 r r e s i s t o r l a d d e r d a 2 o u t p u t e n a b l e b i t d a t a b u s a v s s v ref 0 1 msb 0 1 r 2r r 2r r 2r r 2r r 2r r 2 r r 2r 2r lsb 2r p5 6 /da 1 /pwm 01 d - a 1 c o n v e r s i o n r e g i s t e r d a 1 o u t p u t e n a b l e b i t
3886 group user s manual comparator circuit comparator configuration the comparator circuit consists of resistors, comparators, a com- parator control circuit, the comparator reference input selection bit (bit 7 of address 001d 16 ), a comparator data register (address 002d 16 ), the comparator reference power source input pin (p0 0 / p3 ref ) and analog signal input pins (p3 0 p3 7 ). the analog input pin (p3 0 p3 7 ) also functions as an ordinary digital port. comparator operation to activate the comparator, first set port p3 to input mode by set- ting the corresponding direction register (address 0007 16 ) to 0 to use port p3 as an analog voltage input pin. the internal fixed ana- log voltage (v cc ? 29/32) can be generated by setting 1 to the comparator reference input selection bit (bit 7) of the serial i/o2 control register (address 001d 16 ). (the internal fixed analog volt- age becomes about 4.5 v at v cc = 5.0 v.) when setting 0 to the comparator reference input selection bit, the p0 0 /p3 ref pin be- comes the comparator reference power source input pin and it is possible to input the comparator reference power source option- ally from the external. the voltage comparison is immediately performed by the writing operation to the comparator data register (address 002d 16 ). after 14 cycles of the internal system clock (the time required for the comparison), the comparison result is stored in the comparator data register (address 002d 16 ). if the analog input voltage is greater than the internal reference voltage, each bit of this register is 1 ; if it is less than the internal reference voltage, each bit of this register is 0 . to perform an- other comparison, the voltage comparison must be performed again by writing to the comparator data register (address 002d 16 ). read the result when 14 cycles of or more have passed after the comparator operation starts. the ladder resistor is turned on dur- ing 14 cycles of , which is required for the comparison, and the reference voltage is generated. an unnecessary current is not consumed because the ladder resistor is turned off while the com- parator operation is not performed. since the comparator consists of capacitor coupling, the electric charge is lost if the clock fre- quency is low. keep that the clock frequency is 1 mhz or more during the com- parator operation. do not execute the stp, wit, or port p3 i/o instruction. fig. 54 comparator circuit functional description v s s 8 8 v cc p 3 ( 8 ) p3 7 p 3 6 p3 0 b0 comparator reference input selection bit (bit 7) of serial i/o2 control register(address 001d 16 ) comparator data register (address 002d 16 ) c o m p a r - a t o r l a d d e r r e s i s t o r c o n n e c t i n g s i g n a l c o m p a r a t o r c o n t r o l c i r c u i t comparator connecting signal c o m p a r - a t o r compar- ator p 0 0 / p 3 r e f v c c ? 2 9 / 3 2 1 0 data bus
3886 group user s manual hardware watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. standard operation of watchdog timer when any data is not written into the watchdog timer control reg- ister (address 001e 16 ) after resetting, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 001e 16 ) and an internal reset occurs at an underflow of the watch- dog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 001e 16 ) may be started before an underflow. when the watchdog timer control reg- ister (address 001e 16 ) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit, and watch- dog timer h count source selection bit are read. initial value of watchdog timer at reset or writing to the watchdog timer control register (address 001e 16 ), each watchdog timer h and l is set to ff 16 . fig. 56 structure of watchdog timer control register watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 001e 16 ) per- mits selecting a watchdog timer h count source. when this bit is set to 0 , the count source becomes the underflow signal of watchdog timer l. the detection time is set to f(x in )=131.072 ms at 8 mhz frequency and f(x cin )=32.768 s at 32 khz frequency. when this bit is set to 1 , the count source becomes the signal divided by 16 for f(x in ) (or f(x cin )). the detection time in this case is set to f(x in )= 512 s at 8 mhz frequency and f(x cin )=128 ms at 32 khz frequency. this bit is cleared to 0 after resetting. operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 001e 16 ) per- mits disabling the stp instruction when the watchdog timer is in operation. when this bit is 0 , the stp instruction is enabled. when this bit is 1 , the stp instruction is disabled. once the stp instruction is executed, an internal reset occurs. when this bit is set to 1 , it cannot be rewritten to 0 by program. this bit is cleared to 0 after resetting. fig. 55 block diagram of watchdog timer functional description x in data bus x cin 10 00 01 main clock division ratio selection bits (note) 0 1 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) ff 16 is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: either hi g h-s p eed, middle-s p eed or low-s p eed mode is selected b y bits 7 and 6 of the cpu mode re g ister. stp instruction ff 16 is set when watchdog timer control register is written to. b 0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer h (for read-out of high-order 6 bit) watchdog timer control register (wdtcon : address 001e 16 ) b 7
3886 group user s manual reset circuit to reset the microcomputer, reset pin should be held at an "l" level for 16 cycles or more of x in . then the reset pin is returned to an "h" level (the power source voltage should be between 2.7 v and 5.5 v (4.0 v to 5.5 v for flash memory version), and the oscil- lation should be stable), reset is released. after the reset is completed, the program starts from the address contained in ad- dress fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.54 v for v cc of 2.7 v. for flash memory version, make sure that the reset input voltage is less than 0.8 v for vcc of 4.0 v. fig. 58 reset sequence fig. 57 reset circuit example functional description ( n o t e ) 0 . 2 v c c 0 v 0 v p o w e r o n v cc r e s e t v cc r e s e t power source voltage detection circuit p o w e r s o u r c e v o l t a g e r e s e t i n p u t v o l t a g e n o t e : r e s e t r e l e a s e v o l t a g e ; v c c = 2 . 7 v ( v c c = 4 . 0 v f o r f l a s h m e m o r y v e r s i o n ) r e s e t internal reset d a t a a d d r e s s s y n c x i n : 1 0 . 5 t o 1 8 . 5 c l o c k c y c l e s x i n ? ? ? ? ? f f f cf f f d ad h , l ? ? ? ? ? ad l a d h 1: the frequency relation of f(x in ) and f( ) is f(x in )=8 f( ). 2: the question marks (?) indicate an undefined state that depends on the previous state. r e s e t a d d r e s s f r o m t h e v e c t o r t a b l e . notes
3886 group user s manual hardware fig. 59 internal status at reset functional description n o t e : ? t h e i n i t i a l v a l u e s d e p e n d o n l e v e l o f t h e c n v s s p i n . x : n o t f i x e d s i n c e t h e i n i t i a l v a l u e s f o r o t h e r t h a n a b o v e m e n t i o n e d r e g i s t e r s a n d r a m c o n t e n t s a r e i n d e f i n i t e a t r e s e t , t h e y m u s t b e s e t . p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( p 5 d ) p o r t p 6 ( p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) p o r t p 7 ( p 7 ) p o r t p 7 d i r e c t i o n r e g i s t e r ( p 7 d ) p o r t p 8 ( p 8 ) p o r t p 8 d i r e c t i o n r e g i s t e r ( p 8 d ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c a d d r e s s r e g i s t e r ( s 0 d ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r ( s 2 d ) t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r ( t b / r b ) s e r i a l i / o 1 s t a t u s r e g i s t e r ( s i o 1 s t s ) s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) b a u d r a t e g e n e r a t o r ( b r g ) s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n ) s e r i a l i / o 2 r e g i s t e r ( s i o 2 ) p r e s c a l e r 1 2 ( p r e 1 2 ) t i m e r 1 ( t 1 ) t i m e r 2 ( t 2 ) t i m e r x y m o d e r e g i s t e r ( t m ) p r e s c a l e r x ( p r e x ) t i m e r x ( t x ) p r e s c a l e r y ( p r e y ) t i m e r y ( t y ) d a t a b u s b u f f e r r e g i s t e r 0 ( d b b 0 ) d a t a b u s b u f f e r s t a t u s r e g i s t e r 0 ( d b b s t s 0 ) d a t a b u s b u f f e r c o n t r o l r e g i s t e r ( d b b c o n ) d a t a b u s b u f f e r r e g i s t e r 1 ( d b b 1 ) d a t a b u s b u f f e r s t a t u s r e g i s t e r 1 ( d b b s t s 1 ) c o m p a r a t o r d a t a r e g i s t e r ( c m p d ) p o r t c o n t r o l r e g i s t e r 1 ( p c t l 1 ) p o r t c o n t r o l r e g i s t e r 2 ( p c t l 2 ) p w m 0 h r e g i s t e r ( p w m 0 h ) p w m 0 l r e g i s t e r ( p w m 0 l ) p w m 1 h r e g i s t e r ( p w m 1 h ) p w m 1 l r e g i s t e r ( p w m 1 l ) a d / d a c o n t r o l r e g i s t e r ( a d c o n ) a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 ) d - a 1 c o n v e r s i o n r e g i s t e r ( d a 1 ) d - a 2 c o n v e r s i o n r e g i s t e r ( d a 2 ) a - d c o n v e r s i o n r e g i s t e r 2 ( a d 2 ) i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( i n t s e l ) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) f l a s h m e m o r y c o n t r o l r e g i s t e r ( f c o n ) f l a s h c o m m a n d r e g i s t e r ( f c m d ) p r o c e s s o r s t a t u s r e g i s t e r p r o g r a m c o u n t e r ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 1 0 ) ( 1 1 ) ( 1 2 ) ( 1 3 ) ( 1 4 ) ( 1 5 ) ( 1 6 ) ( 1 7 ) ( 1 8 ) ( 1 9 ) ( 2 0 ) ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) ( 2 5 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) ( 2 9 ) ( 3 0 ) ( 3 1 ) ( 3 2 ) ( 3 3 ) ( 3 4 ) ( 3 5 ) ( 3 6 ) ( 3 7 ) ( 3 8 ) ( 3 9 ) ( 4 0 ) ( 4 1 ) ( 4 2 ) ( 4 3 ) ( 4 4 ) ( 4 5 ) ( 4 6 ) ( 4 7 ) ( 4 8 ) ( 4 9 ) ( 5 0 ) ( 5 1 ) ( 5 2 ) ( 5 3 ) ( 5 4 ) ( 5 5 ) ( 5 6 ) ( 5 7 ) ( 5 8 ) ( 5 9 ) ( 6 0 ) ( 6 1 ) ( 6 2 ) ( 6 3 ) ( 6 4 ) ( 6 5 ) ( 6 6 ) ( 6 7 ) ( 6 8 ) r e g i s t e r c o n t e n t s 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0ffe 16 0fff 16 (ps) (pc h ) (pc l ) a d d r e s s f f 1 6 0 1 1 6 f f 1 6 0 0 1 6 f f 1 6 f f 1 6 f f 1 6 f f 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 a d d r e s sr e g i s t e r c o n t e n t s 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 x x x x x x x x 0001000x x x x x x x x x x x x x x x x x x x x x x x x x 00011010 10000000 11100000 00111111 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 x xx x x x x x x x x x x x x 0 x xx x x x 00001000 1 fffd 16 contents fffc 16 contents ? x x x x x x x x 000000 x x 010010 0 x x x x x x x
3886 group user s manual clock generating circuit the 3886 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer s recommended values. no exter- nal resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock is the frequency of x in divided by 8. after re- set, this mode is selected. (2) high-speed mode the internal clock is half the frequency of x in . (3) low-speed mode the internal clock is half the frequency of x cin . note if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately af- ter power on and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(x in ) > 3f(x cin ). (4) low power dissipation mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is restarted (by setting the main clock stop bit to 0 ), set sufficient time for oscillation to stabilize. oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an h level, and x in and x cin oscillators stop. when the oscillation stabilizing time set after stp instruction released bit is 0, the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1, set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. either x in or x cin divided by 16 is input to the prescaler 12 as count source, and the output of the prescaler 12 is connected to timer 1. set the timer 1 interrupt enable bit to disabled ( 0 ) before executing the stp instruction. oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the cpu (remains at h ) until timer 1 underflows. the internal clock is supplied for the first time, when timer 1 underflows. therefore make sure not to set the timer 1 interrupt request bit to 1 before the stp instruction stops the oscillator. when the oscillator is re- started by reset, apply l level to the reset pin until the oscillation is stable since a wait time will not be generated. (2) wait mode if the wit instruction is executed, the internal clock stops at an h level, but the oscillator does not stop. the internal clock re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. fig. 60 ceramic resonator circuit fig. 61 external clock input circuit functional description x cin x cout x in x out c in c out c cin c cout rf rd v c c v ss x cin x cout x in x out o p e n o pen e x t e r n a l o s c i l l a t i o n c i r c u i t e x t e r n a l o s c i l l a t i o n c i r c u i t v cc v ss
3886 group user s manual hardware fig. 62 system clock generating circuit block diagram (single-chip mode) functional description w i t i n s t r u c t i o n stp instruction t i m i n g f ( i n t e r n a l c l o c k ) s r q s t p i n s t r u c t i o n s r q main clock stop bit s r q 1 / 2 1 / 4 x in x o u t x c o u t x c i n i n t e r r u p t r e q u e s t reset interrupt disable flag l 1 / 2 p o r t x c s w i t c h b i t 1 0 l o w - s p e e d m o d e high-speed or middle-speed mode m i d d l e - s p e e d m o d e high-speed or low-speed mode main clock division ratio selection bits (note 1) n o t e s 1 : e i t h e r h i g h - s p e e d , m i d d l e - s p e e d o r l o w - s p e e d m o d e i s s e l e c t e d b y b i t s 7 a n d 6 o f t h e c p u m o d e r e g i s t e r . w h e n l o w - s p e e d m o d e i s s e l e c t e d , s e t p o r t x c s w i t c h b i t ( b 4 ) t o 1 . 2 : w h e n b i t 6 o f t h e p o r t c o n t r o l r e g i s t e r 2 i s 0 , t h e i n i t i a l v a l u e i s n o t s e t t o t h e p r e s c a l e r 1 2 a n d t i m e r 1 a t s t p i n s t r u c t i o n e x e c u t i o n . m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s ( n o t e 1 ) ff 16 0 1 1 6 p r e s c a l e r 1 2 timer 1 r e s e t o r s t p i n s t r u c t i o n ( n o t e 2 )
3886 group user s manual fig. 63 state transitions of system clock functional description cm 4 : port xc switch bit 0 : i/o port function (stop oscillating) 1 : x cin -x cout oscillating function cm 5 : main clock (x in - x out ) stop bit 0 : operating 1 : stopped cm 7 , cm 6 : main clock division ratio selection bit b7 b6 0 0 : = f(x in )/2 ( high-speed mode) 0 1 : = f(x in )/8 (middle-speed mode) 1 0 : = f(x cin )/2 (low-speed mode) 1 1 : not available note s r e s e t c m 4 1 0 c m 4 0 1 c m 6 1 0 c m 4 1 0 c m 6 1 0 c m 7 1 0 c m 4 1 0 c m 5 1 0 cm 6 1 0 c m 6 1 0 cpu mode register b7 b4 c m 7 0 1 c m 6 1 0 ( c p u m : a d d r e s s 0 0 3 b 1 6 ) c m 7 = 0 c m 6 = 1 c m 5 = 0 ( 1 0 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) m i d d l e - s p e e d m o d e ( f ( ) = 1 . 2 5 m h z ) cm 7 =0 cm 6 =1 cm 5 =0(10 mhz oscillating) cm 4 =1(32 khz oscillating) m i d d l e - s p e e d m o d e ( f ( ) = 1 . 2 5 m h z ) c m 7 = 0 c m 6 = 0 c m 5 = 0 ( 1 0 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) h i g h - s p e e d m o d e ( f ( ) = 5 m h z ) cm 7 =1 cm 6 =0 cm 5 =0(10 mhz oscillating) cm 4 =1(32 khz oscillating) low-speed mode (f( )=16 khz) cm 7 =1 cm 6 =0 cm 5 =1(10 mhz stopped) cm 4 =1(32 khz oscillating) l o w - s p e e d m o d e ( f ( ) = 1 6 k h z ) c m 7 = 0 c m 6 = 0 c m 5 = 0 ( 1 0 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) h i g h - s p e e d m o d e ( f ( ) = 5 m h z ) 1 : switch the mode by the allows shown between the mode blocks. (do not switch between the modes directly without an allow.) 2 : the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mo de i s ended. 3 : timer operates in the wait mode. 4 : when the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and timer 1 in middle/high-speed m ode. 5 : when the stop mode is ended, a delay of approximately 0.25 s occurs by timer 1 and timer 2 in low-speed mode. 6 : wait until oscillation stabilizes after oscillating the main clock x in before the switching from the low-speed mode to middle/high-speed mode. 7 : the example assumes that 10 mhz is being applied to the x in pin and 32 khz to the x cin pin. indicates the internal clock.
3886 group user s manual hardware processor mode single-chip mode, memory expansion mode, and microprocessor mode in the m3886 7m8a/e8a can be selected by changing the contents of the processor mode bits (cm 0 and cm 1 : b1 and b0 of address 003b 16 ). in memory expansion mode and microprocessor mode, memory can be expanded externally through ports p0 to p3. in these modes, ports p0 to p3 lose their i/o port functions and become bus pins. fig. 64 memory maps in various processor modes fig. 65 structure of cpu mode register (1) single-chip mode select this mode by resetting the microcomputer with cnv ss con- nected to v ss . (2) memory expansion mode select this mode by setting the processor mode bits (b1, b0) to 01 in software with cnv ss connected to v ss . this mode enables external memory expansion while maintaining the validity of the in- ternal rom. however, do not set this mode in the m3886 9m8a/mca/mfa and the flash memory version. (3) microprocessor mode select this mode by resetting the microcomputer with cnv ss con- nected to v cc , or by setting the processor mode bits to 10 in software with cnv ss connected to v ss . in microprocessor mode, the internal rom is no longer valid and external memory must be used. do not set this mode in the m3886 9m8a/mca/mfa and the flash memory version. port name port p0 port p1 port p2 port p3 function outputs low-order 8 bits of address. outputs high-order 8 bits of address. operates as i/o pins for data d 7 to d 0 (including instruction code). p3 0 and p3 1 function only as output pins (except that the port latch cannot be read). p3 2 is the onw input pin. p3 3 is the reset out output pin. ( note ) p3 4 is the output pin. p3 5 is the sync output pin. p3 6 is the wr output pin, and p3 7 is the rd out- put pin. table 17 port functions in memory expansion mode and microprocessor mode note : if cnv ss is connected to v ss , the microcomputer goes to single- chip mode after a reset, so that this pin cannot be used as the reset out output pin. functional description x x x x 1 6 0 0 0 0 1 6 0 0 4 0 1 6 0 0 0 8 1 6 0 0 0 0 1 6 y y y y 1 6 ffff 16 0 0 0 8 1 6 0 0 4 0 1 6 ffff 16 i n t e r n a l r a m r e s e r v e d a r e a i n t e r n a l r o m m e m o r y e x p a n s i o n m o d e the shaded area are external memory area. s f r a r e a x x x x 1 6 i n d i c a t e s t h e l a s t a d d r e s s o f i n t e r n a l r a m . y y y y 1 6 i n d i c a t e s t h e f i r s t a d d r e s s o f i n t e r n a l r o m . s f r a r e a m i c r o p r o c e s s o r m o d e * * : i n t e r n a l r a m r e s e r v e d a r e a x x x x 1 6 ** b 0 cpu mode register (cpum : address 003b 16 ) p r o c e s s o r m o d e b i t s ( c m 1 , c m 0 ) b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : m e m o r y e x p a n s i o n m o d e ( n o t e ) 1 0 : m i c r o p r o c e s s o r m o d e ( n o t e ) 1 1 : n o t a v a i l a b l e s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e b 7 n o t e : t h i s i s n o t a v a i l a b l e f o r t h e p r o d u c t s e x c e p t m 3 8 8 6 7 m 8 a / e 8 a .
3886 group user s manual bus control at memory expansion the m3886 7m8a/e8a have a built-in onw function to facilitate access to an external (expanded) memory and i/o devices in memory expansion mode or microprocessor mode. if an l level signal is input to the p3 2 /onw pin when the cpu is in a read or write state, the corresponding read or write cycle is extended by one cycle of . during this extended term, the rd and wr signals remain at l. this extension function is valid only for writing to and reading from addresses 0000 16 to 0007 16 and 0440 16 to ffff 16 , and only read and write cycles are extended. fig. 66 onw function timing functional description r d w r o n w * ** * term where onw input signal is received. during this term, the onw signal must be fixed at either h or l . at all other times, the input level of the onw signal has no affect on operations. the bus cycles is not extended for an address in the area 0008 16 to 043f 16, because the onw signal is not received. r e a d c y c l e w r i t e c y c l e d u m m y c y c l e w r i t e c y c l e r e a d c y c l ed u m m y c y c l e a d 1 5 a d 0
3886 group user s manual hardware eprom mode the built-in prom of the blank one time prom version and built- in eprom version can be read or programmed with a general-purpose prom programmer using a special programming adapter. the one time prom version and the built-in eprom version have the function of the m5m27c101 corresponding for writing to the built-in prom. set the address of prom program- mer in the user rom area. the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 67 is recommended to verify programming. fig. 67 programming and testing of one time prom version table 18 programming adapter package 80p6q-a 80d0 name of programming adapter pca4738h-80a pca4738l-80a table 19 prom programmer setup product name prom programmer setup corresponding device writing area m3886 7e8ahp m3886 7e8afs rom area of microcomputer m5m27c101k byte program 08080 16 | 0fffd 16 8080 16 | fffd 16 functional description p r o g r a m m i n g w i t h p r o m p r o g r a m m e r s c r e e n i n g ( c a u t i o n ) ( 1 5 0 c f o r 4 0 h o u r s ) v e r i f i c a t i o n w i t h p r o m p r o g r a m m e r f u n c t i o n a l c h e c k i n t a r g e t d e v i c e t h e s c r e e n i n g t e m p e r a t u r e i s f a r h i g h e r t h a n t h e s t o r a g e t e m p e r a t u r e . n e v e r e x p o s e t o 1 5 0 c e x c e e d i n g 1 0 0 h o u r s . c a u t i o n :
3886 group user s manual flash memory mode the m3886 9ffahp/gp has the flash memory mode in addition to the normal operation mode (microcomputer mode). the user can use this mode to perform read, program, and erase operations for the internal flash memory. the m3886 9ffahp/gp has three modes the user can choose: the parallel input/output and serial input/output mode, where the flash memory is handled by using the external programmer, and the cpu reprogramming mode, where the flash memory is handled by the central processing unit (cpu). the following ex- plains these modes. (1) flash memory mode 1 (parallel i/o mode) the parallel i/o mode can be selected by connecting wires as shown in figures 68 and supplying power to the v cc and v pp pins. in this mode, the m3886 9ffahp/gp operates as an equiva- lent of mitsubishi s cmos flash memory m5m28f101. however, because the m3886 9ffahp/gp s internal memory has a capacity of 60 kbytes, programming is available for addresses 01000 16 to 0ffff 16 , and make sure that the data in addresses 00000 16 to 00fff 16 and addresses 10000 16 to 1ffff 16 are ff 16 . note also that the m3886 9ffahp/gp does not contain a facility to read out a device identification code by applying a high voltage to address input (a9). be careful not to erratically set program condi- tions when using a general-purpose prom programmer. table 20 shows the pin assignments when operating in the paral- lel input/output mode. table 20 pin assignments of m3886 9ffahp/gp when operating in the parallel input/output mode v cc v pp v ss address input data i/o __ ce ___ oe ___ we m3886 9ffahp/gp v cc cnv ss v ss ports p0, p1, p3 1 port p2 p3 6 p3 7 p3 3 m5m28f101 v cc v pp v ss a 0 a 16 d 0 d 7 __ ce __ oe ___ we functional outline (parallel input/output mode) in the parallel input/output mode, the m3886 9ffahp/gp allow the user to choose an operation mode between the read-only mode and the read/write mode (software command control mode) de- pending on the voltage applied to the v pp pin. when v pp = v pp l, the read-only mode is selected, and the user can choose one of three states (e.g., read, output disable, or standby) depending on ___ ___ ___ inputs to the ce, oe, and we pins. when v pp = v pp h, the read/ write mode is selected, and the user can choose one of four states (e.g., read, output disable, standby, or write) depending on inputs __ __ ___ to the ce, oe, and we pins. table 21 shows assignment states of control input and each state. read __ the microcomputer enters the read state by driving the ce, and __ ___ oe pins low and the we pin high; and the contents of memory corresponding to the address to be input to address input pins (a 0 a 16 ) are output to the data input/output pins (d 0 d 7 ). output disable the microcomputer enters the output disable state by driving the __ ___ __ ce pin low and the we and oe pins high; and the data input/out- put pins enter the floating state. standby __ the microcomputer enters the standby state by driving the ce pin high. the m3886 9ffahp/gp is placed in a power-down state consuming only a minimal supply current. at this time, the data in- put/output pins enter the floating state. write the microcomputer enters the write state by driving the v pp pin ___ __ high (v pp = v pp h) and then the we pin low when the ce pin is __ low and the oe pin is high. in this state, software commands can be input from the data input/output pins, and the user can choose program or erase operation depending on the contents of this soft- ware command. pin mode read output disable standby read output disable standby write read-only read/write __ ce v il v il v ih v il v il v ih v il v il v ih v il v ih v ih table 21 assignment sates of control input and each state __ oe ___ we v ih v ih v ih v ih v il v pp l v pp l v pp l v pp h v pp h v pp h v pp h v pp output floating floating output floating floating input data i/o note: can be v il or v ih . state functional description
3886 group user s manual hardware supply 5 v 10 % to v cc and 0 v to v ss . connect to 5 v 10 % in read-only mode, connect to 11.7 to 12.6 v in read/write mode. connect to v ss . connect a ceramic resonator between x in and x out . connect to v ss . connect to v ss . port p0 functions as 8-bit address input (a 0 a 7 ). port p1 functions as 8-bit address input (a 8 a 15 ). function as 8-bit data s i/o pins (d 0 d 7 ). __ __ ___ p3 7 , p3 6 and p3 3 function as the oe, ce and we input pins respectively. p3 1 functions as the a 16 input pin. connect p3 0 and p3 2 to v ss . input h or l to p3 4 , p3 5 , or keep them open. connect p4 4 , p4 6 to v ss . input h or l to p4 0 - p4 3, p4 5 , p4 7 , or keep them open. input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. power supply v pp input reset input clock input clock output analog supply input reference voltage input address input (a 0 a 7 ) address input (a 8 a 15 ) data i/o (d 0 d 7 ) control signal input input port p4 input port p5 input port p6 input port p7 input port p8 table 22 pin description (flash memory parallel i/o mode) pin name input input input output input input input i/o input input input input input input input /output functions v cc , v ss cnv ss _____ reset x in x out av ss v ref p0 0 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 p3 7 p4 0 p4 7 p5 0 p5 7 p6 0 p6 7 p7 0 p7 7 p8 0 p8 7 functional description
3886 group user s manual fig. 68 pin connection of m3886 9ffahp/gp when operating in parallel input/output mode functional description 1 2 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 56 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 4 1 4 2 43 4 4 4 5 4 6 4 7 48 4 9 50 51 52 5 3 54 5 5 5 6 57 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 69 7 0 7 1 72 7 3 74 7 5 7 6 7 7 7 8 79 8 0 p 3 0 / p w m 0 0 p 3 1 / p w m 1 0 p6 2 /an 2 p 6 1 / a n 1 p 6 0 / a n 0 p 7 7 / s c l p 7 6 / s d a p 7 5 / i n t 4 1 p 7 4 / i n t 3 1 p 7 2 / s c l k 2 p 7 1 / s o u t 2 p 7 0 / s i n 2 p 5 7 / d a 2 / p w m 1 1 p 5 0 / a 0 p 4 5 / t x d p4 4 /r x d p 4 3 / i n t 1 / o b f 0 1 p 6 3 / a n 3 p 6 4 / a n 4 p 6 5 / a n 5 p 6 6 / a n 6 a v s s p6 7 /an 7 v ref v c c p 8 0 / d q 0 p8 1 /dq 1 p 8 2 / d q 2 p 8 3 / d q 3 p 8 4 / d q 4 p 8 5 / d q 5 p 8 6 / d q 6 p 8 7 / d q 7 p 4 2 / i n t 0 / o b f 0 0 cnv s s x in x out v ss r e s e t p 7 3 / s r d y 2 / i n t 2 1 p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 6 / d a 1 / p w m 0 1 p4 0 /x cou t p 4 1 / x c i n p 4 7 / s r d y 1 / s 1 p 5 2 / i n t 3 0 / r p 5 3 / i n t 4 0 / w p 5 1 / i n t 2 0 / s 0 p 3 4 p 3 5 p 0 0 / p 3 r e f p 0 4 p 0 5 p 0 6 p 0 7 p 1 1 p 1 2 p 1 3 p 1 4 p 1 5 p1 6 p1 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 p 1 0 p 0 1 p 0 2 p 3 2 p 3 3 p 3 6 p 3 7 p 0 3 p2 7 p 4 6 / s c l k 1 / o b f 1 0 m3886 9ffahp m3886 9ffagp v p p d 7 a 1 4 d 0 d 1 d 2 d 3 d 4 d 5 d6 a 1 5 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 1 0 a 1 1 a 1 2 a 1 3 v s s vcc o e c e w e a 1 6 * : c o n n e c t t o t h e c e r a m i c o s c i l l a t i o n c i r c u i t . i n d i c a t e s t h e f l a s h m e m o r y p i n . *
3886 group user s manual hardware read-only mode the microcomputer enters the read-only mode by applying v pp l to the v pp pin. in this mode, the user can input the address of a memory location to be read and the control signals at the timing shown in figure 69, and the m3886 9ffahp/gp will output the contents of the user s specified address from data i/o pin to the external. in this mode, the user cannot perform any operation other than read. fig. 69 read timing read/write mode the microcomputer enters the read/write mode by applying v pp h to the v pp pin. in this mode, the user must first input a software command to choose the operation (e. g., read, program, or erase) to be performed on the flash memory (this is called the first cycle), and then input the information necessary for execution of the com- mand (e.g, address and data) and control signals (this is called the second cycle). when this is done, the m3886 9ffahp/gp ex- ecutes the specified operation. table 23 shows the software commands and the input/output in- formation in the first and the second cycles. the input address is ___ latched internally at the falling edge of the we input; software commands and other input data are latched internally at the rising ___ edge of the we input. the following explains each software command. refer to figures 70 to 72 for details about the signal input/output timings. table 23 software command (parallel input/output mode) symbol read program program verify erase erase verify reset device identification address input verify address first cycle data input 00 16 40 16 c0 16 20 16 a0 16 ff 16 90 16 address input read address program address adi second cycle data i/o read data (output) program data (input) verify data (output) 20 16 (input) verify data (output) ff 16 (input) ddi (output) note: adi = device identification address : manufacturer s code 00000 16 , device code 00001 16 ddi = device identification data : manufacturer s code 1c 16 , device code d0 16 x can be v il or v ih . functional description address valid address t rc t a(ce) t wrr t df t a(oe) t dh t olz floating floating t clz t a(ad) v ih v il v ih v il v ih v il v ih v il v oh v ol ce oe we data dout
3886 group user s manual read command the microcomputer enters the read mode by inputting command code 00 16 in the first cycle. the command code is latched into ___ the internal command latch at the rising edge of the we input. when the address of a memory location to be read is input in the second cycle, with control signals input at the timing shown in figure 70, the m3886 9ffahp/gp outputs the contents of the specified address from the data i/o pins to the external. the read mode is retained until any other command is latched into the command latch. consequently, once the m3886 9ffahp/gp en- ters the read mode, the user can read out the successive memory contents simply by changing the input address and executing the second cycle only. any command other than the read command must be input beginning from its command code over again each time the user execute it. the contents of the command latch immedi- ately after power-on is 00 16 . fig. 70 timings during reading functional description address valid address t wc t ch t cs t rc t a(ce) t df t wrr t wp t rrw t a(oe) t dh t dh t vsc t clz t olz t ds t a(ad) v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp dout 00 16
3886 group user s manual hardware program command the microcomputer enters the program mode by inputting com- mand code 40 16 in the first cycle. the command code is latched ___ into the internal command latch at the rising edge of the we input. when the address which indicates a program location and data is input in the second cycle, the m3886 9ffahp/gp internally ___ latches the address at the falling edge of the we input and the ___ data at the rising edge of the we input. the m3886 9ffahp/gp ___ starts programming at the rising edge of the we input in the sec- ond cycle and finishes programming within 10 s as measured by its internal timer. programming is performed in units of bytes. note: a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in this verification, the user must re- peatedly execute the program command until the pass. refer to figure 73 for the programming flowchart. program verify command the microcomputer enters the program verify mode by inputting command code c0 16 in the first cycle. this command is used to verify the programmed data after executing the program com- mand. the command code is latched into the internal command ___ latch at the rising edge of the we input. when control signals are input in the second cycle at the timing shown in figure 71, the m3886 9ffahp/gp outputs the programmed address s contents to the external. since the address is internally latched when the pro- gram command is executed, there is no need to input it in the second cycle. fig. 71 input/output timings during programming (verify data is output at the same timing as for read.) functional description address program program verify program address t wc t cs t rrw t wp t wph t wp t dp t ds 40 16 d in c0 16 dout t ds t dh t dh verify data output t dh t vsc t ds t wp t wrr t cs t cs t ch t ch t ch t as t ah v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp
3886 group user s manual erase command the erase command is executed by inputting command code 20 16 in the first cycle and command code 20 16 again in the second cycle. the command code is latched into the internal command ___ latch at the rising edges of the we input in the first cycle and in the second cycle, respectively. the erase operation is initiated at ___ the rising edge of the we input in the second cycle, and the memory contents are collectively erased within 9.5 ms as mea- sured by the internal timer. note that data 00 16 must be written to all memory locations before executing the erase command. note: an erase operation is not completed by executing the erase command once. always be sure to execute an erase verify command after executing the erase command. when the fail- ure is found in this verification, the user must repeatedly ex- ecute the erase command until the pass. refer to figure 73 for the erase flowchart. fig. 72 input/output timings during erasing (verify data is output at the same timing as for read.) erase verify command the user must verify the contents of all addresses after complet- ing the erase command. the microcomputer enters the erase verify mode by inputting the verify address and command code a0 16 in the first cycle. the address is internally latched at the fall- ___ ing edge of the we input, and the command code is internally ___ latched at the rising edge of the we input. when control signals are input in the second cycle at the timing shown in figure 72, the m3886 9ffahp/gp outputs the contents of the specified address to the external. note: if any memory location where the contents have not been erased is found in the erase verify operation, execute the op- eration of erase erase verify over again. in this case, however, the user does not need to write data 00 16 to memory locations before erasing. functional description address erase erase verify verify address t wc t cs t rrw t wp t wph t wp t de t ds 20 16 20 16 a0 16 dout t ds t dh t dh verify data output t dh t vsc t ds t wp t wrr t cs t cs t ch t ch t ch t as t ah v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp
3886 group user s manual hardware reset command the reset command provides a means of stopping execution of the erase or program command safely. if the user inputs command code ff 16 in the second cycle after inputting the erase or program command in the first cycle and again input command code ff 16 in the third cycle, the erase or program command is disabled (i.e., reset), and the m3886 9ffahp/gp is placed in the read mode. if the reset command is executed, the contents of the memory does not change. device identification code command by inputting command code 90 16 in the first cycle, the user can read out the device identification code. the command code is latched into the internal command latch at the rising edge of the ___ we input. at this time, the user can read out manufacture s code 1c 16 (i.e., mitsubishi) by inputting 0000 16 to the address input pins in the second cycle; the user can read out device code d0 16 (i. e., 1m-bit flash memory) by inputting 0001 16 . these command and data codes are input/output at the same tim- ing as for read. functional description
3886 group user s manual fig. 73 programming/erasing algorithm flow chart functional description start v cc = 5 v, v pp = v pp h adrs = first location x = 0 write program command write program data duration = 10 s x = x + 1 write program-verify command 40 16 d in c0 16 00 16 duration = 6 s x = 25 ? last adrs ? no inc adrs write read command v pp = v pp l device passed device failed verify byte ? verify byte ? fail fail program erase yes yes no pass pass start v cc = 5 v, v pp = v pp h adrs = first location x = 0 write erase command program all bytes = 00 16 all bytes = 00 16 ? write erase command duration = 9.5 ms x = x + 1 write erase-verify command 20 16 20 16 a0 16 00 16 duration = 6 s x = 1000 ? last adrs ? no inc adrs write read command v pp = v pp l device passed device failed verify byte ? verify byte ? fail fail yes yes no pass pass yes no
3886 group user s manual hardware table 24 dc electrical characteristics (t a = 25 ?, v cc = 5 v ?10 %, unless otherwise noted) symbol max. 1 100 15 15 15 10 100 100 30 30 0.8 v cc 0.45 v cc + 1.0 12.6 __ v cc = 5.5 v, ce = v ih v cc = 5.5 v, __ ce = v cc 0.2 v __ v cc = 5.5 v, ce = v il , t rc = 150 ns, i out = 0 ma v pp = v pp h v pp = v pp h 0 v pp v cc v cc hardware 1-78 3886 group user s manual (2) flash memory mode 2 (serial i/o mode) the m3886 9ffahp/gp has a function to serially input/output the software commands, addresses, and data required for operation on the internal flash memory (e. g., read, program, and erase) us- ing only a few pins. this is called the serial i/o (input/output) mode. this mode can be selected by driving the sda (serial data __ input/output), sclk (serial clock input ), and oe pins high after connecting wires as shown in figures 74 and powering on the v cc pin and then applying v pp h to the v pp pin. in the serial i/o mode, the user can use six types of software com- mands: read, program, program verify, erase, erase verify and error check. serial input/output is accomplished synchronously with the clock, beginning from the lsb (lsb first). fig. 74 pin connection of m3886 9ffahp/gp when operating in serial i/o mode functional description 1 234 789101 11 2131 41 51 61 71819 2 0 56 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 32 33 3 4 3 5 36 3 7 3 8 39 4 0 4 1 4 2 43 44 45 4 6 47 48 4 9 5 0 5 1 5 2 5 3 54 55 5 6 57 5 8 59 6 0 6 1 6 2 63 6 4 6 5 66 67 6 8 6 9 7 0 7 1 72 73 7 4 75 76 77 78 79 80 p 3 0 / p w m 0 0 p 3 1 / p w m 1 0 p6 2 /an 2 p6 1 /an 1 p 6 0 / a n 0 p 7 7 / s c l p 7 6 / s d a p 7 5 / i n t 4 1 p 7 4 / i n t 3 1 p 7 2 / s c l k 2 p 7 1 / s o u t 2 p 7 0 / s i n 2 p 5 7 / d a 2 / p w m 1 1 p 5 0 / a 0 p 4 5 / t x d p 4 4 / r x d p 4 3 / i n t 1 / o b f 0 1 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 a v s s p6 7 /an 7 v ref v c c p8 0 /dq 0 p8 1 /dq 1 p8 2 /dq 2 p8 3 /dq 3 p8 4 /dq 4 p8 5 /dq 5 p8 6 /dq 6 p8 7 /dq 7 p 4 2 / i n t 0 / o b f 0 0 cnv s s x in x out v ss r e s e t p 7 3 / s r d y 2 / i n t 2 1 p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 6 / d a 1 / p w m 0 1 p4 0 /x cou t p4 1 /x cin p 4 7 / s r d y 1 / s 1 p 5 2 / i n t 3 0 / r p 5 3 / i n t 4 0 / w p 5 1 / i n t 2 0 / s 0 p 3 4 p 3 5 p 0 0 / p 3 r e f p 0 4 p 0 5 p 0 6 p 0 7 p 1 1 p 1 2 p 1 3 p 1 4 p 1 5 p1 6 p1 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 p 1 0 p 0 1 p 0 2 p 3 2 p 3 3 p 3 6 p 3 7 p 0 3 p2 7 p 4 6 / s c l k 1 / o b f 1 0 m3886 9ffahp m3886 9ffagp v p p o e vss v c c s d a b u s y s c l k * :connect to the ceramic oscillation circuit. indicates the flash memory pin . *
3886 group user s manual hardware table 27 pin description (flash memory serial i/o mode) v cc , v ss cnv ss _____ reset x in x out av ss v ref p0 0 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 p3 6 p3 7 p4 0 p4 3 , p4 5 p4 4 p4 6 p4 7 p5 0 p5 7 p6 0 p6 7 p7 0 p7 7 p8 0 p8 7 pin power supply v pp input reset input clock input clock output analog supply input reference voltage input input port p0 input port p1 input port p2 input port p3 control signal input input port p4 sda i/o sclk input busy output input port p5 input port p6 input port p7 input port p8 name input input input output input input input input input input input i/o input output input input input input input /output functions supply 5 v 10 % to v cc and 0 v to v ss . connect to 11.7 to 12.6 v. connect to v ss . connect a ceramic resonator between x in and x out . connect to v ss . input an arbitrary level between the range of v ss and v cc . input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. __ oe input pin input h or l to p4 0 - p4 3 , p4 5 , or keep them open. this pin is for serial data i/o. this pin is for serial clock input. this pin is for busy signal output. input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. input h or l , or keep them open. functional description
3886 group user s manual functional outline (serial i/o mode) in the serial i/o mode, data is transferred synchronously with the clock using serial input/output. the input data is read from the sda pin into the internal circuit synchronously with the rising edge of the serial clock pulse; the output data is output from the sda pin synchronously with the falling edge of the serial clock pulse. data is transferred in units of eight bits. in the first transfer, the user inputs the command code. this is fol- lowed by address input and data input/output according to the contents of the command. table 28 shows the software com- mands used in the serial i/o mode. the following explains each software command. table 28 software command (serial i/o mode) read program program verify erase erase verify error check number of transfers command first command code input 00 16 40 16 c0 16 20 16 a0 16 80 16 read address l (input) program address l (input) verify data (output) 20 16 (input) verify address l (input) error code (output) second read address h (input) program address h (input) verify address h (input) third fourth read data (output) program data (input) verify data (output) input command code 00 16 in the first transfer. proceed and input the low-order 8 bits and the high-order 8 bits of the address and __ pull the oe pin low. when this is done, the m3886 9ffahp/gp reads out the contents of the specified address, and then latches __ it into the internal data latch. when the oe pin is released back high and serial clock is input to the sclk pin, the read data that has been latched into the data latch is serially output from the sda pin. fig. 75 timings during reading functional description l sclk busy oe sda t ch a 0 a 7 a 8 a 15 d 0 d 7 t ch t cr command code input (00 16 ) read address input (l) read address input (h) read data output t wr read t rc note : when outputting the read data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000000
3886 group user s manual hardware input command code 40 16 in the first transfer. proceed and input the low-order 8 bits and the high-order 8 bits of the address and then program data. programming is initiated at the last rising edge of the serial clock during program data transfer. the busy pin is driven high during program operation. programming is completed within 10 s as measured by the internal timer, and the busy pin is pulled low. note : a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in the verification, the user must re- peatedly execute the program command until the pass in the verification. refer to figure 73 for the programming flowchart. input command code c0 16 in the first transfer. proceed and drive __ the oe pin low. when this is done, the m3886 9ffahp/gp verify- reads the programmed address s contents, and then latches it into __ the internal data latch. when the oe pin is released back high and serial clock is input to the sclk pin, the verify data that has been latched into the data latch is serially output from the sda pin. fig. 77 timings during program verify fig. 76 timings during programming functional description sclk busy oe sda t ch a 0 00000010 a 7 a 8 a 15 d 0 d 7 t ch t ch t pc command code input (40 16 ) program address input (l) program address input (h) program data input t wp program sclk busy oe sda d 0 d 7 t crpv command code input (c0 16 ) verify data output t wr verify read t rc note: when outputting the verify data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000011 l
3886 group user s manual input command code 20 16 in the first transfer and command code 20 16 again in the second transfer. when this is done, the m3886 9ffahp/gp executes an erase command. erase is initi- ated at the last rising edge of the serial clock. the busy pin is driven high during the erase operation. erase is completed within 9.5 ms as measured by the internal timer, and the busy pin is pulled low. note that data 00 16 must be written to all memory loca- tions before executing the erase command. note: a erase operation is not completed by executing the erase command once. always be sure to execute a erase verify command after executing the erase command. when the fail- ure is found in the verification, the user must repeatedly ex- ecute the erase command until the pass in the verification. refer to figure 73 for the erase flowchart. fig. 78 timings at erasing the user must verify the contents of all addresses after complet- ing the erase command. input command code a0 16 in the first transfer. proceed and input the low-order 8 bits and the high-order __ 8 bits of the address and pull the oe pin low. when this is done, the m3886 9ffahp/gp reads out the contents of the specified ad- __ dress, and then latches it into the internal data latch. when the oe pin is released back high and serial clock is input to the sclk pin, the verify data that has been latched into the data latch is serially output from the sda pin. note: if any memory location where the contents have not been erased is found in the erase verify operation, execute the op- eration of erase erase verify over again. in this case, however, the user does not need to write data 00 16 to memory locations before erasing. fig. 79 timings during erase verify functional description tw e sclk busy oe sda t ch t ec 00000100 00000100 command code input (20 16 ) command code input (20 16 ) erase h l sclk busy oe sda t ch a 0 a 7 a 8 a 15 d 0 d 7 t ch t crev command code input (a0 16 ) verify address input (l) verify address input (h) verify data output t wr verify read t rc note : when outputting the verify data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000101
3886 group user s manual hardware input command code 80 16 in the first transfer, and the m3886 9ffahp/gp outputs error information from the sda pin, beginning at the next falling edge of the serial clock. if the lsb bit of the 8-bit error information is 1, it indicates that a command error has occurred. a command error means that some invalid com- mands other than commands shown in table 28 has been input. when a command error occurs, the serial communication circuit sets the corresponding flag and stops functioning to avoid an erro- neous programming or erase. when being placed in this state, the serial communication circuit does not accept the subsequent serial clock and data (even including an error check command). there- fore, if the user wants to execute an error check command, temporarily drop the v pp pin input to the v pp l level to terminate the serial input/output mode. then, place the m3886 9ffahp/gp into the serial i/o mode back again. the serial communication cir- cuit is reset by this operation and is ready to accept commands. the error flag alone is not cleared by this operation, so the user can examine the serial communication circuit s error conditions before reset. this examination is done by the first execution of an error check command after the reset. the error flag is cleared when the user has executed the error check command. because the error flag is undefined immediately after power-on, always be sure to execute the error check command. fig. 80 timings at error checking note: the programming/erasing algorithm flow chart of the serial i/o mode is the same as that of the parallel i/o mode. re- fer to figure 73. functional description sclk busy oe sda e0 t ch command code input (80 16 ) error flag output 00000001 ?????? note: when outputting the error flag, the sda pin is switched for output at the first falling edge of the serial clock. the sda pin i s placed in the floating state during the period of th (c-e) after the last rising edge of the serial clock (at the 8th bit). ? h l
3886 group user s manual dc electrical characteristics (ta = 25 c, v cc = 5 v ?10 %, v pp = 11.7 to 12.6 v, unless otherwise noted) i cc , i pp -relevant standards during read, program, and erase are the same as in the parallel input/output mode. v ih , v il , v oh , v ol , i ih , and __ i il for the sclk, sda, busy, oe pins conform to the microcomputer modes. table 29 ac electrical characteristics (t a = 25 c, v cc = 5 v ?10 %, v pp = 11.7 to 12.6 v, f(x in ) = 10 mhz, unless otherwise noted) symbol max. 10 9.5 90 250 (note 4) t ch t cr t wr t rc t crpv t wp t pc t crev t we t ec t c(ck) t w(ckh) t w(ckl) t r(ck) t f(ck) t d(c-q) t h(c-q) t h(c-e) t su(d-c) t h(c-d) serial transmission interval read waiting time after transmission read pulse width transfer waiting time after read waiting time before program verify programming time transfer waiting time after programming waiting time before erase verify erase time transfer waiting time after erase sclk input cycle time sclk high-level pulse width sclk low-level pulse width sclk rise time sclk fall time sda output delay time sda output hold time sda output hold time (only the 8th bit) sda input set up time sda input hold time parameter ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit min. 500 (note 1) 500 (note 1) 400 (note 2) 500 (note 1) 6 500 (note 1) 6 500 (note 1) 250 100 100 20 20 0 0 150 (note 3) 30 90 limits notes 1: when f(x in ) = 10 mhz or less, calculate the minimum value according to formula 1. formula 1 : 10 6 2: when f(x in ) = 10 mhz or less, calculate the minimum value according to formula 2. formula 2 : 10 6 3: when f(x in ) = 10 mhz or less, calculate the minimum value according to formula 3. formula 3 : 10 6 4: when f(x in ) = 10 mhz or less, calculate the minimum value according to formula 4 formula 4 : 10 6 5000 f(x in ) 4000 f(x in ) 2500 f(x in ) 1500 f(x in ) ac waveforms functional description sclk sda input test conditions for ac characteristics output timing voltage : v ol = 0.8 v, v oh = 2.0 v input timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc sda output t c(ck) t r(ck) t d(c-q) t su(d-c) t h(c-d) t h(c-e) t h(c-q) t f(ck) t w(ckl) t w(ckh)
3886 group user s manual hardware (3) flash memory mode 3 (cpu reprogramming mode) the m3886 9ffahp/gp has the cpu reprogramming mode where a built-in flash memory is handled by the central processing unit (cpu). in cpu reprogramming mode, the flash memory is handled by writing and reading to/from the flash memory control register (see figure 81) and the flash command register (see figure 82). the cnv ss pin is used as the v pp power supply pin in cpu repro- gramming mode. it is necessary to apply the power-supply voltage of v pp h from the external to this pin. functional outline (cpu reprogramming mode) figure 81 shows the flash memory control register bit configura- tion. figure 82 shows the flash command register bit configuration. bit 0 of the flash memory control register is the cpu reprogram- ming mode select bit. when this bit is set to 1 and v pp h is applied to the cnvss/v pp pin, the cpu reprogramming mode is selected. whether the cpu reprogramming mode is realized or not is judged by reading the cpu reprogramming mode monitor flag (bit 2 of the flash memory control register). bit 1 is a busy flag which becomes 1 during erase and program execution. whether each operation has been completed or not is judged by checking this flag after execution of each erase or program com- mand. bits 4, 5 of the flash memory control register are the erase/pro- gram area select bits. these bits specify an area where erase and program is operated. when the erase command is executed after an area is specified by these bits, only the specified area is erased. programming is enabled only for the specified area: pro- gramming is disabled for all other areas. when cpu reprogramming mode is valid, the area not specified by the erase/program area select bits cannot be read out. transfer the cpu reprogramming mode control program to inter- nal ram before entering the cpu reprogramming mode, and then execute this program on internal ram. if an interrupt occurs while this program is being executed, the flash memory area is accessed, but normal operations cannot be performed because the flash memory area cannot be read out. execute processes such as interrupt disable during the cpu re- programming mode control program. figure 83 shows the cpu mode register bit configuration in the cpu reprogramming mode. set bits 1 and 0 to 00 (single-chip mode) in the cpu reprogramming mode. fig. 81 flash memory control register bit configuration functional description 76543210 0 0 flash memory control register (fcon : address 0ffe 16 ) cpu reprogramming mode select bit (note) 0 : cpu reprogramming mode is invalid. (normal operation mode) 1 : when applying 0 v or v pp l to cnv ss /v pp pin, cpu reprogramming mode is invalid. when applying v pp h to cnv ss /v pp pin, cpu reprogramming mode is valid. erase/program busy flag 0 : erase and program are completed or not have been executed. 1 : erase/program is being executed. cpu reprogramming mode monitor flag 0 : cpu reprogramming mode is invalid. 1 : cpu reprogramming mode is valid. erase/program area select bits 0 0 : addresses 1000 16 to ffff 16 (total 60 kbytes) 0 1 : addresses 1000 16 to 7fff 16 (total 28 kbytes) 1 0 : addresses 8000 16 to ffff 16 (total 32 kbytes) 1 1 : not available fix this bit to 0. fix this bit to 0. note: bit 0 can be reprogrammed only when 0 v is applied to the cnv ss /v pp pin. not used (returns "0" when read)
3886 group user s manual the operation procedure in cpu reprogramming mode is de- scribed below. < beginning procedure > ? apply 0 v to the cnvss/v pp pin for reset release. ? after cpu reprogramming mode control program is transferred to internal ram, jump to this control program on ram. (the follow- ing operations are controlled by this control program). ? set 1" to the cpu reprogramming mode select bit. ? apply v pp h to the cnv ss /v pp pin. ? wait till cnv ss /v pp pin becomes 12 v. ? read the cpu reprogramming mode monitor flag to confirm whether the cpu reprogramming mode is valid. ? the operation of the flash memory is executed by software-com- mand-writing to the flash command register . note: the following are necessary other than this: control for data which is input from the external (serial i/o etc.) and to be programmed to the flash memory initial setting for ports etc. writing to the watchdog timer < release procedure > ? apply 0v to the cnv ss /v pp pin. ? wait till cnv ss /v pp pin becomes 0v. ? set the cpu reprogramming mode select bit to 0. each software command is explained as follows. when 00 16 " is written to the flash command register, the m3886 9ffahp/gp enters the read mode. the contents of the corresponding address can be read by reading the flash memory (for instance, with the lda instruction etc.) under this condition. the read mode is maintained until another command code is written to the flash command register. accordingly, after setting the read mode once, the contents of the flash memory can continuously be read. after reset and after the reset command is executed, the read mode is set. fig. 82 flash command register bit configuration fig. 83 cpu mode register bit configuration in cpu rewriting mode functional description writing of software command 00 16 40 16 c0 16 20 16 + 20 16 a0 16 ff 16 + ff 16 read command program command program verify command erase command erase verify command reset command note: the flash command register is write-only register. flash command register (fcmd : address 0fff 16 ) 76 5 4 3 2 1 0 p r o c e s s o r m o d e b i t s b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : n o t a v a i l a b l e 1 x : n o t a v a i l a b l e p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n x c o u t o s c i l l a t i n g f u n c t i o n m a i n c l o c k ( x i n x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 7 b 6 0 0 : = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : = f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) 1 1 : n o t a v a i l a b l e 00 1 c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7 b0 s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e f i x t h i s b i t t o 1 .
3886 group user s manual hardware when 40 16 is written to the flash command register, the m3886 9ffahp/gp enters the program mode. subsequently to this, if the instruction (for instance, sta instruction) for writing byte data in the address to be programmed is executed, the control circuit of the flash memory executes the program. the erase/program busy flag of the flash memory control register is set to 1 when the program starts, and becomes 0 when the program is completed. accordingly, after the write in- struction is executed, cpu can recognize the completion of the program by polling this bit. the programmed area must be specified beforehand by the erase/ program area select bits. during programming, watchdog timer stops with ffff 16 set. note: a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in this verification, the user must re- peatedly execute the program command until the pass. refer to figure 84 for the flow chart of the programming. when c0 16 is written to the flash command register, the m3886 9ffahp/gp enters the program verify mode. subsequently to this, if the instruction (for instance, lda instruction) for reading byte data from the address to be verified (i.e., previously pro- grammed address), the contents which has been written to the address actually is read. cpu compares this read data with data which has been written by the previous program command. in consequence of the compari- son, if not agreeing, the operation of program program verify must be executed again. when writing 20 16 twice continuously to the flash command reg- ister, the flash memory control circuit performs erase to the area specified beforehand by the erase/program area select bits. erase/program busy flag of the flash memory control register be- comes 1 when erase begins, and it becomes 0 when erase completes. accordingly, cpu can recognize the completion of erase by polling this bit. data 00 16 must be written to all areas to be erased by the pro- gram and the program verify commands before the erase command is executed. during erasing, watchdog timer stops with ffff 16 set. note: the erasing operation is not completed by executing the erase command once. always be sure to execute an erase verify command after executing the erase command. when the fail- ure is found in this verification, the user must repeatedly ex- ecute the erase command until the pass. refer to figure 84 for the erasing flowchart. when a0 16 is written to the flash command register, the m3886 9ffahp/gp enters the erase verify mode. subsequently to this, if the instruction (for instance, lda instruction) for reading byte data from the address to be verified, the contents of the ad- dress is read. cpu must erase and verify to all erased areas in a unit of ad- dress. if the address of which data is not ff 16 (i.e., data is not erased) is found, it is necessary to discontinue erasure verification there, and execute the operation of erase erase verify again. note: by executing the operation of erase erase verify again when the memory not erased is found. it is unnecessary to write data 00 16 before erasing in this case. the reset command is a command to discontinue the program or erase command on the way. when ff 16 is written to the command register two times continuously after 40 16 or 20 16 is written to the flash command register, the program, or erase command becomes invalid (reset), and the m3886 9ffahp/gp enters the reset mode. the contents of the memory does not change even if the reset com- mand is executed. dc electric characteristics note: the characteristic concerning the flash memory part are the same as the characteristic of the parallel i/o mode. ac electric characteristics note: the characteristics are the same as the characteristic of the microcomputer mode. functional description
3886 group user s manual fig. 84 flowchart of program/erase operation at cpu reprogramming mode functional description erase program busy flag = 0 start adrs = first location x = 0 write program command write program data wait 1 s x = x + 1 write program-verify command 40 16 din c0 16 00 16 duration = 6 s x = 25 ? last adrs ? no inc adrs write read command device passed device failed verify byte ? verify byte ? fail fail program erase yes yes no pass pass start adrs = first location x = 0 write erase command program all bytes = 00 16 all bytes = 00 16 ? write erase command x = x + 1 write erase-verify command 20 16 20 16 a0 16 00 16 duration = 6 s x = 1000 ? last adrs ? no inc adrs write read command device passed device failed verify byte ? verify byte ? fail fail yes yes no pass pass yes no erase program busy flag = 0 wait 1 s no yes yes no
3886 group user s manual hardware notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1 , then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is 1 the instruction with the addressing mode which uses the value of a direction register as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy1 signal, set the transmit enable bit, the receive enable bit, and the s rdy1 output enable bit to 1. serial i/o1 continues to output the final bit from the t x d pin after transmission is completed. s out2 pin for serial i/o2 goes to high impedance after transfer is completed. when in serial i/o1 (clock-synchronous mode) or in serial i/o2, an external clock is used as synchronous clock, write transmission data to the transmit buffer register or serial i/o2 register, during transfer clock is h. a-d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 500 khz during an a-d conversion. do not execute the stp instruction during an a-d conversion. d-a converter the accuracy of the d-a converter becomes rapidly poor under the v cc = 4.0 v or less condition; a supply voltage of v cc 4.0 v is recommended. when a d-a converter is not used, set all values of d-ai conversion registers (i=1, 2) to 00 16 . instruction execution time the instruction execution time is obtained by multiplying the pe- riod of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the period of the internal clock is half of the x in period in high- speed mode. when the onw function is used in modes other than single-chip mode, the period of the internal clock may be four times that of the x in . notes on programming
3886 group user s manual notes on usage handling of power source pins in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin), between power source pin (v cc pin) and analog power source input pin (av ss pin). connect the same kind of capacitor between program power source pin (cnvss/vpp) and gnd pin when executing on-board reprogramming of flash memory version. make sure the connec- tion between each pin is as short as possible. we recommend using a ceramic capacitor of 0.01 f to 0.1 f. eprom version/one time prom version/ flash memory version the cnv ss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnv ss pin and v ss pin or v cc pin with 1 to 10 k ? resistance. the mask rom version track of cnv ss pin has no operational in- terference even if it is connected to vss pin or vcc pin via a resistor. erasing of flash memory version for the parallel i/o mode and the serial i/o mode, set addresses 01000 16 to 0ffff 16 as the memory area to be erased. if an incor- rect address is set as the memory area to be erased, the product may be permanently damaged. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom confirmation form ? 1 2.mark specification form ? 2 3.data to be written to rom, in eprom form (three identical cop- ies) data required for one time prom programming orders the following are necessary when ordering a prom programming service: 1.rom programming confirmation form ? 1 2.mark specification form ? 2 3.data to be programmed to prom, in eprom form (three identi- cal copies) for the mask rom confirmation, the rom programming confirma- tion, and the mark specifications, refer to the mitsubishi mcu technical information homepage. ? 1 mask rom confirmation forms http://www.infomicom.mesc.co.jp/38000/38ordere.htm ? 2 mark specification forms http://www.infomicom.mesc.co.jp/mela/markform.htm notes on usage/data required for mask orders and one time prom programming orders
3886 group user s manual hardware functional description supplement functional description supplement a-d converter a-d conversion is started by setting ad conversion completion bit to 0. during a-d conversion, internal operations are performed as follows. 1. after the start of a-d conversion, a-d conversion register goes to 00 16 . 2. the highest-order bit of a-d conversion register is set to 1, and the comparison voltage vref is input to the comparator. then, v ref is compared with analog input voltage v in . 3. as a result of comparison, when v ref < v in , the highest-order bit of a-d conversion register becomes 1. when v ref > v in , the highest-order bit becomes 0. by repeating the above operations up to the lowest-order bit of the a-d conversion register, an analog value converts into a digital value. a-d conversion completes at 61 clock cycles (15.25 s at f(x in ) = 8 mhz) after it is started, and the result of the conversion is stored into the a-d conversion register. concurrently with the completion of a-d conversion, a-d conversion interrupt request occurs, so that the ad conversion interrupt request bit is set to 1. table 30 relative formula for a reference voltage v ref of a-d converter and v ref v ref 1024 ? ? a result of the first comparison to the tenth comparison table 31 change of a-d conversion register during a-d conversion at start of conversion first comparison second comparison third comparison after completion of tenth comparison 0 a result of a-d conversion ? 1 change of a-d conversion register 0 value of comparison voltage (v ref ) v ref 2 v ref 2 v ref 4 v ref 2 v ref 4 v ref 8 when n = 0 v ref = 0 when n = 1 to 1023 v ref = ? n n: value of a-d converter (decimal numeral) v ref 2 v ref 4 v ref 1024 0 0 000 0 000 1 0 0 00 0 0 0 0 0 10 0 0 0 0 000 ? 1 ? 2 00 0 0 0 0 0 1 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10
3886 group user s manual figures 85 shows the a-d conversion equivalent circuit, and figure 86 shows the a-d conversion timing chart. fig. 85 a-d conversion equivalent circuit fig. 86 a-d conversion timing chart functional description supplement v ss v cc av ss v cc an 0 an 1 an 2 an 3 an 4 v ref av ss v ref v in c b1 b0 b4 b2 about 2 kw sampling clock a-d control register built-in d-a converter reference clock chopper amplifier a-d conversion register (high-order) a-d conversion register (low-order) ad conversion interrupt request w r i t e s i g n a l f o r a - d c o n t r o l r e g i s t e r a d c o n v e r s i o n c o m p l e t i o n b i t sampling clock
3886 group user? manual application 2.1 i/o port 2-2 2.1 i/o port this paragraph explains the registers setting method and the notes relevant to the i/o ports. 2.1.1 memory map fig. 2.1.1 memory map of registers relevant to i/o port 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) port p8 (p8)/port p4 input register (p4i) port p8 direction register (p8d)/port p7 input register (p7i) port control register 1 (pctl1) port control register 2 (pctl2) 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 002e 16 002f 16
3886 group user s manual application 2-3 2.1 i/o port 2.1.2 relevant registers fig. 2.1.2 structure of port pi (i = 0 to 8) fig. 2.1.3 structure of port pi direction register (i = 0 to 8) port pi b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi 0 port pi 1 port pi 2 port pi 3 port pi 4 port pi 5 port pi 6 port pi 7 in output mode write read port latch in input mode write : port latch read : value of pins port pi (pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8) [address : 00 16 , 02 16 , 04 16 , 06 16, 08 16 , 0a 16 , 0c 16, 0e 16 , 10 16 ] ? ? ? ? ? ? ? ? port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi direction register 0 0 0 0 0 0 0 0 port pi direction register (pid) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8) [address : 01 16 , 03 16 , 05 16 , 07 16, 09 16 , 0b 16 , 0d 16 , 0f 16 , 11 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ? ? ? ? ? ? ? ?
3886 group user s manual application 2.1 i/o port 2-4 fig. 2.1.4 structure of port control register 1 fig. 2.1.5 structure of port control register 2 port control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 port control register 1 (pctl1) [address 2e 16 ] pwm 1 enable bit p0 0 p0 3 output structure selection bit 0: pwm 0 output disabled 1: pwm 0 output enabled p1 4 p1 7 output structure selection bit 0: cmos 1: n-channel open-drain p0 4 p0 7 output structure selection bit p1 0 p1 3 output structure selection bit p3 0 p3 3 pull-up control bit p3 4 p3 7 pull-up control bit pwm 0 enable bit 0: cmos 1: n-channel open-drain 0: cmos 1: n-channel open-drain 0: cmos 1: n-channel open-drain 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 0: pwm 1 output disabled 1: pwm 1 output enabled port control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 port control register 2 (pctl2) [address 2f 16 ] port output p4 2 /p4 3 clear function selection bit p4 input level selection bit (p4 2 p4 6 ) 0: automatic set 01 16 to timer 1 and ff 16 to prescaler 12 1: no automatic set p8 function selection bit 0: cmos level input 1: ttl level input p7 input level selection bit (p7 0 p7 5 ) p4 output structure selection bit (p4 2 , p4 3 , p4 4 , p4 6 ) int 2 , int 3 , int 4 interrupt switch bit timer y count source selection bit oscillation stabilizing time set after stp instruction released bit 0: cmos level input 1: ttl level input 0: cmos 1: n-channel open-drain 0: port p8/port p8 direction register 1: port p4 input register/port p7 input register 0: int 20 , int 30 , int 40 interrupt 1: int 21 , int 31 , int 41 interrupt 0: f(x in )/16 (f(x cin )/16 in low- speed mode) 1: f(x cin ) 0: only software clear 1: software clear and output data bus buffer 0 reading (system bus side)
3886 group user s manual application 2-5 2.1 i/o port 2.1.3 port p4/p7 input register port p4 input register/port p7 input register is selected by setting the port p8 function selection bit of port control register 2 to 1 . by reading port p4/p7 input register, the contents of pins can be read out even if the pins are set as output pins. that is, the port state can be read out when the output h voltage is falling or the output l voltage is rising. n-channel open-drain output structure is selected by setting the p4 output structure selection bit of port control register 2 to 1 . ttl level input is selected by setting the p4 input level selection bit and the p7 input level selection bit of port control register 2 to 1 . pull-up is selected by setting the p3 0 p3 3 pull-up control bit and the p3 4 p3 7 pull-up control bit of port control register 1 to 1 . 2.1.4 handling of unused pins table 2.1.1 handling of unused pins (in single-chip mode) pins/ports name p0, p1, p2, p3, p4, p5, p6, p7, p8 v ref av ss x out pins/ports name p3 0 , p3 1 p4, p5, p6, p7, p8 v ref onw reset out sync av ss x out handling open. set to the input mode and connect each to vcc or vss through a resistor of 1 k ? to 10 k ? . set to the output mode and open at l or h level. connect to vss (gnd). connect to vcc through a resistor of 1 k ? to 10 k ? . open. open. open. connect to vss (gnd). open, only when using an external clock. table 2.1.2 handling of unused pins (in memory expansion mode, microprocessor mode) handling set to the input mode and connect each to vcc or vss through a resistor of 1 k ? to 10 k ? . set to the output mode and open at l or h level. connect to vss (gnd). connect to vss (gnd). open, only when using an external clock.
3886 group user s manual application 2.1 i/o port 2-6 2.1.5 notes on input and output pins (1) notes in stand-by state in stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an i/o port undefined , especially for i/o ports of the n-channel open-drain. pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: external circuit variation of output levels during the ordinary operation when using built-in pull-up or pull-down resistor, note on varied current values. when setting as an input port: fix its input level when setting as an output port: prevent current from flowing out to external reason in i/o ports of the n-channel open-drain, in spite of setting as an output port with its direction register, when the content of the port latch is 1 , the transistor becomes the off state, which causes the ports to be the high-impedance state. note that the level becomes undefined depending on external circuits. accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input port and an i/o port are undefined . this may cause power source current. * 1 stand-by state : the stop mode by executing the stp instruction the wait mode by executing the wit instruction (2) modifying output data with bit managing instruction when the port latch of an i/o port is modified with the bit managing instruction* 2 , the value of the unspecified bit may be changed. reason the bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the port latch of an i/o port, the following is executed to all bits of the port latch. as for a bit which is set for an input port : the pin state is read in the cpu, and is written to this bit after bit managing. as for a bit which is set for an output port : the bit value of the port latch is read in the cpu, and is written to this bit after bit managing. note the following : even when a port which is set as an output port is changed for an input port, its port latch holds the output data. as for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. * 2 bit managing instructions : seb , and clb instructions
3886 group user s manual application 2-7 2.1 i/o port 2.1.6 termination of unused pins (1) terminate unused pins ? output ports : open ? input ports : connect each pin to v cc or v ss through each resistor of 1 k ? to 10 k ? . with regard to ports which can select the built-in pull-up resistor, the built-in pull-up resistor can be used. as for pins whose potential affects to operation modes such as cnv ss pin or others, select the v cc pin or the v ss pin according to their operation mode. ? i/o ports : set the i/o ports for the input mode and connect them to v cc or v ss through each resistor of 1 k ? to 10 k ? . with regard to ports which can select the built-in pull-up resistor, the built-in pull- up resistor can be used. set the i/o ports for the output mode and open them at l or h . when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the system, thoroughly perform system evaluation on the user side. since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. ? the avss pin when not using the a-d/d-a converter : when not using the a-d/d-a converter, handle a power source pin for the a-d/d-a converter, avss pin as follows: avss: connect to the vss pin (2) termination remarks ? input ports and i/o ports : do not open in the input mode. reason the power source current may increase depending on the first-stage circuit. an effect due to noise may be easily produced as compared with proper termination ? and ? shown on the above. ? i/o ports : when setting for the input mode, do not connect to v cc or v ss directly. reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and v cc (or v ss ). ? i/o ports : when setting for the input mode, do not connect multiple ports in a lump to v cc or v ss through a resistor. reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.
3886 group user? manual application 2.2 interrupt 2.2 interrupt this paragraph explains the registers setting method and the notes relevant to the interrupt. 2.2.1 memory map fig. 2.2.1 memory map of registers relevant to interrupt 2.2.2 relevant registers fig. 2.2.2 structure of port control register 2 003f 16 interrupt control register 1 (icon1) interrupt request register 2 (ireq2) interrupt request register 1 (ireq1) 003e 16 003d 16 003c 16 003b 16 interrupt edge selection register (intedge) interrupt source selection register (intsel) 003a 16 0039 16 port control register 2 (pctl2) 002f 16 interrupt control register 2 (icon2) port control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function a t reset rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 port control register 2 (pctl2) [address 2f 16 ] p o r t o u t p u t p 4 2 / p 4 3 c l e a r f u n c t i o n s e l e c t i o n b i t p 4 i n p u t l e v e l s e l e c t i o n b i t ( p 4 2 p 4 6 ) 0 : a u t o m a t i c s e t 0 1 1 6 t o t i m e r 1 a n d f f 1 6 t o p r e s c a l e r 1 2 1 : n o a u t o m a t i c s e t p 8 f u n c t i o n s e l e c t i o n b i t 0 : c m o s l e v e l i n p u t 1 : t t l l e v e l i n p u t p 7 i n p u t l e v e l s e l e c t i o n b i t ( p 7 0 p 7 5 ) p 4 o u t p u t s t r u c t u r e s e l e c t i o n b i t ( p 4 2 , p 4 3 , p 4 4 , p 4 6 ) int 2 , int 3 , int 4 interrupt switch bit t i m e r y c o u n t s o u r c e s e l e c t i o n b i t o s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r s t p i n s t r u c t i o n r e l e a s e d b i t 0 : c m o s l e v e l i n p u t 1 : t t l l e v e l i n p u t 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n 0 : p o r t p 8 / p o r t p 8 d i r e c t i o n r e g i s t e r 1 : p o r t p 4 i n p u t r e g i s t e r / p o r t p 7 i n p u t r e g i s t e r 0: int 20 , int 30 , int 40 interrupt 1: int 21 , int 31 , int 41 interrupt 0 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) 1 : f ( x c i n ) 0 : o n l y s o f t w a r e c l e a r 1 : s o f t w a r e c l e a r a n d o u t p u t d a t a b u s b u f f e r 0 r e a d i n g ( s y s t e m b u s s i d e )
3886 group user s manual application 2-9 2.2 interrupt fig. 2.2.3 structure of interrupt source selection register fig. 2.2.4 structure of interrupt edge selection register i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t s o u r c e s e l e c t i o n b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 0 i n t e r r u p t 1 : i n p u t b u f f e r f u l l i n t e r r u p t int 2 /i 2 c interrupt source selection bit cntr 1 /key-on wake-up interrupt source selection bit 0 : i n t 1 i n t e r r u p t 1 : o u t p u t b u f f e r e m p t y i n t e r r u p t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t c n t r 0 / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : s e r i a l i / o 1 t r a n s m i t i n t e r r u p t 1 : s c l , s d a i n t e r r u p t 0 : c n t r 0 i n t e r r u p t 1 : s c l , s d a i n t e r r u p t s e r i a l i / o 2 / i 2 c i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : serial i/o2 interrupt 1 : i 2 c interrupt 0 : int 2 interrupt 1 : i 2 c interrupt 0 : c n t r 1 i n t e r r u p t 1 : k e y - o n w a k e - u p i n t e r r u p t a d c o n v e r t e r / k e y - o n w a k e - u p i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : a - d c o n v e r t e r i n t e r r u p t 1 : k e y - o n w a k e - u p i n t e r r u p t ? 1 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 2 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 3 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r [ i n t s e l : a d d r e s s 0 0 3 9 1 6 ] ? 1 ? 2 ? 2 ? 3 ? 3 ? 1 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r b7 b6 b5 b4 b3 b2 b1 b0 b function a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt edge selection register (intedge) [address : 3a 16 ] n o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . t h e s e a r e w r i t e d i s a b l e d b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active i n t 3 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 2 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active ? ? ? n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . i n t 4 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : falling edge active 1 : rising edge active
3886 group user s manual application 2.2 interrupt fig. 2.2.6 structure of interrupt request register 2 fig. 2.2.5 structure of interrupt request register 1 i n t e r r u p t r e q u e s t r e g i s t e r 2 b7 b6 b5 b4 b3 b2 b1 b0 b function a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . ? c n t r 0 / s c l , s d a i n t e r r u p t r e q u e s t b i t c n t r 1 / k e y - o n w a k e - u p i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued int 4 interrupt request bit ad converter/key-on wake-up interrupt request bit ? : t h e s e b i t s c a n b e c l e a r e d t o 0 b y p r o g r a m , b u t c a n n o t b e s e t t o 1 . 0 : no interrupt request issued 1 : interrupt request issued s e r i a l i / o 2 / i 2 c i n t e r r u p t r e q u e s t b i t i n t 2 / i 2 c i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued i n t 3 i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? interrupt request register 1 b 7b 6b5b 4b 3b 2b 1b 0 b function a t reset rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s : 3 c 1 6 ] i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t r e q u e s t b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued t i m e r y i n t e r r u p t r e q u e s t b i t timer 1 interrupt request bit ? : t h e s e b i t s c a n b e c l e a r e d t o 0 b y p r o g r a m , b u t c a n n o t b e s e t t o 1 . 0 : no interrupt request issued 1 : interrupt request issued s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued t i m e r x i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? timer 2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ?
3886 group user s manual application 2-11 2.2 interrupt fig. 2.2.7 structure of interrupt control register 1 interrupt control register 1 b 7b 6b5b 4b 3b 2b 1b 0 b f u n c t i o n a t reset rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s : 3 e 1 6 ] i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t e n a b l e b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled timer y interrupt enable bit timer 1 interrupt enable bit s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled t i m e r 2 i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled fig. 2.2.8 structure of interrupt control register 2 i n t e r r u p t c o n t r o l r e g i s t e r 2 b 7b 6b5b 4b 3b 2b 1b 0 b function a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] f i x t h i s b i t t o 0 . c n t r 0 / s c l , s d a i n t e r r u p t e n a b l e b i t cntr 1 /key-on wake-up interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled int 4 interrupt enable bit a d c o n v e r t e r / k e y - o n w a k e - u p i n t e r r u p t e n a b l e b i t s e r i a l i / o 2 / i 2 c i n t e r r u p t e n a b l e b i t i n t 2 / i 2 c i n t e r r u p t e n a b l e b i t i n t 3 i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0
3886 group user s manual application 2.2 interrupt 2.2.3 interrupt source the 3886 group permits interrupts of 16 sources among 21 sources. these are vector interrupts with a fixed priority system. accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. this priority is determined by hardware, but a variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. for interrupt sources, vector addresses and interrupt priority, refer to table 2.2.1. table 2.2.1 interrupt sources, vector addresses and priority of 3886 group interrupt request generating conditions remarks interrupt source low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) reset (note 2) int 0 input buffer full (ibf) int 1 output buffer empty (obe) serial i/o1 reception serial i/o1 transmission s cl , s da timer x timer y timer 1 timer 2 cntr 0 s cl , s da cntr 1 key-on wake-up serial i/o2 i 2 c int 2 i 2 c int 3 int 4 a-d converter key-on wake-up brk instruction at reset at detection of either rising or falling edge of int 0 input at input data bus buffer writing at detection of either rising or falling edge of int 1 input at output data bus buffer read- ing at completion of serial i/o1 data reception at completion of serial i/o1 transfer shift or when transmis- sion buffer is empty at detection of either rising or falling edge of s cl or s da at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of s cl or s da at detection of either rising or falling edge of cntr 1 input at falling of port p3 (at input) in- put logical level and at completion of serial i/o2 data transfer at completion of data transfer at detection of either rising or falling edge of int 2 input at completion of data transfer at detection of either rising or falling edge of int 3 input at detection of either rising or falling edge of int 4 input at completion of a-d conversion at falling of port p3 (at input) in- put logical level and at brk instruction execution non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o1 is selected valid when serial i/o1 is selected external interrupt (active edge selectable) stp release timer underflow external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (falling edge valid) valid when serial i/o2 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (falling edge valid) non-maskable software interrupt
3886 group user s manual application 2-13 2.2 interrupt 2.2.4 interrupt operation when an interrupt request is accepted, the contents of the following registers just before acceptance of the interrupt requests is automatically pushed onto the stack area in the order of ? , ? and ? . ? high-order contents of program counter (pc h ) ? low-order contents of program counter (pc l ) ? contents of processor status register (ps) after the contents of the above registers are pushed onto the stack area, the accepted interrupt vector address enters the program counter and consequently the interrupt processing routine is executed. when the rti instruction is executed at the end of the interrupt processing routine, the contents of the above registers pushed onto the stack area are restored to the respective registers in the order of ? , ? and ? ; and the microcomputer resumes the processing executed just before acceptance of the interrupts. figure 2.2.9 shows an interrupt operation diagram. fig. 2.2.9 interrupt operation diagram i n t e r r u p t o c c u r s ( a c c e p t i n g i n t e r r u p t r e q u e s t ) e x e c u t i n g r o u t i n e s u s p e n d e d o p e r a t i o n r e s u m e p r o c e s s i n g : operation commanded by software : i n t e r n a l o p e r a t i o n p e r f o r m e d a u t o m a t i c a l l y contents of program counter (high-order) are pushed onto stack contents of program counter (low-order) are pushed onto stack contents of processor status register are pushed onto stack c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r a r e p o p p e d f r o m s t a c k contents of program counter (low-order) are popped from stack contents of program counter (high-order) are popped from stack rti instruction i n t e r r u p t p r o c e s s i n g r o u t i n e
3886 group user s manual application 2.2 interrupt (1) processing upon acceptance of interrupt request upon acceptance of an interrupt request, the following operations are automatically performed. ? the processing being executed is stopped. ? the contents of the program counter and the processor status register are pushed onto the stack area. figure 2.2.10 shows the changes of the stack pointer and the program counter upon acceptance of an interrupt request. ? concurrently with the push operation, the jump destination address (the beginning address of the interrupt processing routine) of the occurring interrupt stored in the vector address is set in the program counter, then the interrupt processing routine is executed. ? after the interrupt processing routine is started, the corresponding interrupt request bit is automatically cleared to 0 . the interrupt disable flag is set to 1 so that multiple interrupts are disabled. accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination address in the vector area corresponding to each interrupt. fig. 2.2.10 changes of stack pointer and program counter upon acceptance of interrupt request interrupt disable flag = 0 p r o g r a m c o u n t e r stack pointer program counter (low-order) p r o g r a m c o u n t e r ( h i g h - o r d e r ) pc l p c h ( s ) s p r o g r a m c o u n t e r s t a c k p o i n t e r pc l p c h (s) 3 s vector address (from interrupt vector area) i n t e r r u p t d i s a b l e f l a g = 1 interrupt request is accepted s t a c k a r e a (s) processor status register p r o g r a m c o u n t e r ( l o w - o r d e r ) program counter (high-order) (s) ( s ) 3 s t a c k a r e a
3886 group user s manual application 2-15 2.2 interrupt (2) timing after acceptance of interrupt request the interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently being executed. figure 2.2.11 shows the time up to execution of interrupt processing routine and figure 2.2.12 shows the timing chart after acceptance of interrupt request. fig. 2.2.12 timing chart after acceptance of interrupt request fig. 2.2.11 time up to execution of interrupt processing routine i n t e r r u p t r e q u e s t g e n e r a t e d main routine i n t e r r u p t p r o c e s s i n g r o u t i n e 7 t o 2 3 c y c l e s ( w h e n f ( x i n ) = 8 m h z , 1 . 7 5 s t o 5 . 7 5 s ) 2 cycle s 5 c y c l e s s t a r t o f i n t e r r u p t p r o c e s s i n g 0 t o 1 6 c y c l e s waiting time for post-processing of pipeline stack push and vector fetch ? ? w h e n e x e c u t i n g d i v i n s t r u c t i o n p c h pc l p sa l a h s, sps s-2, sps s-1, sps pc b l b h a l , a h : c p u o p e r a t i o n c o d e f e t c h c y c l e (t h i s i s a n i n t e r n a l s i g n a l t h a t c a n n o t b e o b s e r v e d f r o m t h e e x t e r n a l u n i t . ) : v e c t o r a d d r e s s o f e a c h i n t e r r u p t : j u m p d e s t i n a t i o n a d d r e s s o f e a c h i n t e r r u p t : 0 0 1 6 o r 0 1 1 6 s y n c b l , b h a l , a h s p s data bus n o t u s e d a d d r e s s b u s s y n c r d w r
3886 group user s manual application 2.2 interrupt 2.2.5 interrupt control the acceptance of all interrupts, excluding the brk instruction interrupt, can be controlled by the interrupt request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. figure 2.2.13 shows an interrupt control diagram. fig. 2.2.13 interrupt control diagram the interrupt request bit, interrupt enable bit and interrupt disable flag function independently and do not affect each other. an interrupt is accepted when all the following conditions are satisfied. interrupt request bit .......... 1 interrupt enable bit ........... 1 interrupt disable flag ........ 0 though the interrupt priority is determined by hardware, a variety of priority processing can be performed by software using the above bits and flag. table 2.2.2 shows a list of interrupt control bits according to the interrupt source. (1) interrupt request bits the interrupt request bits are allocated to the interrupt request register 1 (address 3c 16 ) and interrupt request register 2 (address 3d 16 ). the occurrence of an interrupt request causes the corresponding interrupt request bit to be set to 1 . the interrupt request bit is held in the 1 state until the interrupt is accepted. when the interrupt is accepted, this bit is automatically cleared to 0 . each interrupt request bit can be set to 0 , but cannot be set to 1 , by software. (2) interrupt enable bits the interrupt enable bits are allocated to the interrupt control register 1 (address 003e 16 ) and the interrupt control register 2 (address 3f 16 ). the interrupt enable bits control the acceptance of the corresponding interrupt request. when an interrupt enable bit is 0 , the corresponding interrupt request is disabled. if an interrupt request occurs when this bit is 0 , the corresponding interrupt request bit is set to 1 but the interrupt is not accepted. in this case, unless the interrupt request bit is set to 0 by software, the interrupt request bit remains in the 1 state. when an interrupt enable bit is 1 , the corresponding interrupt is enabled. if an interrupt request occurs when this bit is 1 , the interrupt is accepted (when interrupt disable flag = 0 ). each interrupt enable bit can be set to 0 or 1 by software. i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t i n t e r r u p t d i s a b l e f l a g b r k i n s t r u c t i o n r e s e t i n t e r r u p t r e q u e s t
3886 group user s manual application 2-17 2.2 interrupt (3) interrupt disable flag the interrupt disable flag is allocated to bit 2 of the processor status register. the interrupt disable flag controls the acceptance of interrupt request except brk instruction. when this flag is 1 , the acceptance of interrupt requests is disabled. when the flag is 0 , the acceptance of interrupt requests is enabled. this flag is set to 1 with the sei instruction and is set to 0 with the cli instruction. when a main routine branches to an interrupt processing routine, this flag is automatically set to 1 , so that multiple interrupts are disabled. to use multiple interrupts, set this flag to 0 with the cli instruction within the interrupt processing routine. figure 2.2.14 shows an example of multiple interrupts. table 2.2.2 list of interrupt bits according to interrupt source int 0 /input buffer full int 1 /output buffer empty serial i/o1 reception serial i/o1 transmission/s cl , s da timer x timer y timer 1 timer 2 cntr 0 /s cl , s da cntr1/key-on wake-up serial i/o2/i 2 c int 2 /i 2 c int 3 int 4 a-d converter/key-on wake-up interrupt enable bit address 003e 16 003e 16 003e 16 003e 16 003e 16 003e 16 003e 16 003e 16 003f 16 003f 16 003f 16 003f 16 003f 16 003f 16 003f 16 bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 interrupt request bit address 003c 16 003c 16 003c 16 003c 16 003c 16 003c 16 003c 16 003c 16 003d 16 003d 16 003d 16 003d 16 003d 16 003d 16 003d 16 bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 interrupt source
3886 group user s manual application 2.2 interrupt fig. 2.2.14 example of multiple interrupts reset i = 1 i n t e r r u p t 1 i = 1 i = 0 i = 1 rti i n t e r r u p t r e q u e s t 1 i n t e r r u p t r e q u e s t nesting t i m e multiple interrupt c1 = 1 c2 = 1 i = 0 i n t e r r u p t r e q u e s t 2 m a i n r o u t i n e i n t e r r u p t 2 r t i : i n t e r r u p t d i s a b l e f l a g : i n t e r r u p t e n a b l e b i t o f i n t e r r u p t 1 : i n t e r r u p t e n a b l e b i t o f i n t e r r u p t 2 : s e t a u t o m a t i c a l l y . : s e t b y s o f t w a r e . i c1 c2 i = 0 i = 0 c 1 = 0 , c 2 = 0
3886 group user s manual application 2-19 2.2 interrupt 2.2.6 int interrupt the int interrupt requests is generated when the microcomputer detects a level change of each int pin (int 0 int 4 ). (1) active edge selection int 0 int 4 can be selected from either a falling edge or rising edge detection as an active edge by the interrupt edge selection register. in the 0 state, the falling edge of the corresponding pin is detected. in the 1 state, the rising edge of the corresponding pin is detected. (2) int 0 ?nt 2 interrupt sources selection which of interrupt source of the following interrupt sources can be selected by the interrupt source selection register (address 39 16 ). (set each bit to 0 when using int.) int 0 or input buffer full (bit 0) int 1 or output buffer empty (bit 1) int 2 or i 2 c (bit 5) (3) int 2 ?nt 4 input pins selection the occurrence sources of the external interrupt int 2 to int 4 can be selected from which of the following by the int 2 , int 3 , int 4 interrupt switch bit of the port control register 2 (address 2f 16 ). int 20 , int 30 , int 40 or int 21 , int 31 , int 41
3886 group user s manual application 2.2 interrupt 2.2.7 key input interrupt a key input interrupt request is generated by applying l level to any port p3 pin that has been set to the input mode. in other words, it is generated when and of the input level goes from 1 to 0 . (1) connection example when key input interrupt is used when using the key input interrupt, compose an active-low key matrix which inputs to port p3. figure 2.2.15 shows a connection example and the port p3 block diagram when using a key input interrupt. in the connection example in figure 2.2.15, a key input interrupt request is generated by pressing one of the keys corresponding to ports p3 0 to p3 3 . fig. 2.2.15 connection example and port p3 block diagram when using key input interrupt ? ? ? ? ?? ? ? ? ? ?? ? ? ? ? ?? ? ? ? ? ? ? p o r t p 3 0 l a t c h port p3 0 direction register = 0 port p3 1 latch port p3 1 direction register = 0 p o r t p 3 2 l a t c h port p3 2 direction register = 0 port p3 3 latch port p3 3 direction register = 0 p o r t p 3 4 l a t c h port p3 4 direction register = 1 port p3 5 latch port p3 5 direction register = 1 port p3 6 latch port p3 6 direction register = 1 p o r t p 3 7 l a t c h p o r t p 3 7 d i r e c t i o n r e g i s t e r = 1 p3 0 input p 3 1 i n p u t p 3 2 i n p u t p 3 3 i n p u t p3 4 output p3 5 output p 3 6 o u t p u t p 3 7 o u t p u t port p3 input reading circuit comparator circuit p o r t p x x l l e v e l o u t p u t [ p - c h a n n e l t r a n s i s t o r f o r p u l l - u p [ [ c m o s o u t p u t b u f f e r k e y i n p u t i n t e r r u p t r e q u e s t port control register 1 bit 4 = 1 p o r t p 3 0 l a t c h port p3 0 direction register = 0 port p3 1 latch port p3 1 direction register = 0 p o r t p 3 2 l a t c h port p3 2 direction register = 0 port p3 3 latch port p3 3 direction register = 0 p o r t p 3 4 l a t c h port p3 4 direction register = 1 port p3 5 latch port p3 5 direction register = 1 port p3 6 latch port p3 6 direction register = 1 p o r t p 3 7 l a t c h p o r t p 3 7 d i r e c t i o n r e g i s t e r = 1 p3 0 input p 3 1 i n p u t p 3 2 i n p u t p 3 3 i n p u t p3 4 output p3 5 output p 3 6 o u t p u t p 3 7 o u t p u t p o r t c o n t r o l r e g i s t e r 1 b i t 5 = 0 port p3 input reading circuit comparator circuit p o r t p x x l l e v e l o u t p u t ? p - c h a n n e l t r a n s i s t o r f o r p u l l - u p ? ? c m o s o u t p u t b u f f e r k e y i n p u t i n t e r r u p t r e q u e s t port control register 1 bit 4 = 1
3886 group user s manual application 2-21 2.2 interrupt (2) relevant registers setting figure 2.2.16 shows the relevant registers setting (corresponding to figure 2.2.15). fig. 2.2.16 registers setting relevant to key input interrupt (corresponding to figure 2.2.15) (3) key input interrupt source selection when using a key input interrupt source, select which of the following by the interrupt source selection register (address 39 16 ). cntr 0 or key-on wake-up (bit 6) a-d converter or key-on wake-up (bit 7) p 3 d 0 10 1 ireq2 b 0 b 7 b 0 b 7 key-on wake-up interrupt request (note 2) p o r t p 3 d i r e c t i o n r e g i s t e r ( a d d r e s s 0 7 1 6 ) bits corresponding to p3 7 to p3 0 interrupt request register 2 (address 3d 16 ) 1 p c t l 1 1 b 0 b 7 p o r t c o n t r o l r e g i s t e r 1 ( a d d r e s s 2 e 1 6 ) p3 0 to p3 3 pull-up 10 0 i n t s e l b 0 b 7 i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( a d d r e s s 3 9 1 6 ) key-on wake-up interrupt n o t e 1 n o t e 2 n o t e 2 n o t e 1 i c o n 2 b 0 b 7 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( a d d r e s s 3 f 1 6 ) n o t e 3 n o t e 3 0 key-on wake-up interrupt: enabled (note 3) n o t e s 1 : s e t 1 t o t h e b i t w h i c h i s s e l e c t e d a s t h e k e y - o n w a k e - u p i n t e r r u p t s o u r c e f r o m e i t h e r b 7 o r b 6 o f t h e i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r . d o n o t s e t 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ( w h e n s e t t i n g 1 t o b 6 , s e t 0 t o b 7 . w h e n s e t t i n g 0 t o b 6 , s e t 1 t o b 7 . ) 2 : w h e n s e t t i n g 1 t o b 7 o f t h e i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r , s e t 0 t o b 6 o f t h e i n t e r r u p t r e q u e s t r e g i s t e r 2 . w h e n s e t t i n g 1 t o b 6 o f t h e i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r , s e t 0 t o b 1 o f t h e i n t e r r u p t r e q u e s t r e g i s t e r 2 . 3 : w h e n s e t t i n g 1 t o b 7 o f t h e i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r , s e t 1 t o b 6 o f t h e i n t e r r u p t c o n t r o l r e g i s t e r 2 . w h e n s e t t i n g 1 t o b 6 o f t h e i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r , s e t 1 t o b 1 o f t h e i n t e r r u p t c o n t r o l r e g i s t e r 2 . 0 : i n p u t p o r t 1 : o u t p u t p o r t
3886 group user s manual application 2.2 interrupt 2.2.8 notes on interrupts (1) switching external interrupt detection edge when switching the external interrupt detection edge, switch it in the following sequence. clear an interrupt enable bit to 0 (interrupt disabled) switch the detection edge clear an interrupt request bit to 0 (no interrupt request issued) set the interrupt enable bit to 1 (interrupt enabled) fig. 2.2.17 sequence of switching detection edge the interrupt circuit recognizes the switching of the detection edge as the change of external input signals. this may cause an unnecessary interrupt. (2) check of interrupt request bit when executing the bbc or bbs instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to 0 by using a data transfer instruction, execute one or more instructions before executing the bbc or bbs instruction. clear the interrupt request bit to 0 (no interrupt issued) (one or more instructions) execute the bbc or bbs instruction data transfer instruction: ldm, lda, sta, stx, and sty instructions fig. 2.2.18 sequence of check of interrupt request bit if the bbc or bbs instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to 0 , the value of the interrupt request bit before being cleared to 0 is read.
3886 group user s manual application 2-23 2.2 interrupt (3) change of relevant register settings when the setting of the following registers or bits is changed, the interrupt request bit may be set to 1 . interrupt edge selection register (address 3a 16 ) interrupt source selection register (address 39 16 ) int2, int3, int4 interrupt switch bit of port control register 2 (bit 4 of address 2f 16 ) set the above listed registers or bits as the following sequence. clear an interrupt enable bit to 0 (interrupt disabled) set the above listed registers or bits clear an interrupt request bit to 0 (no interrupt request issued) set the interrupt enable bit to 1 (interrupt enabled) fig. 2.2.19 sequence of changing relevant register
3886 group user? manual application 2.3 timer 2.3 timer this paragraph explains the registers setting method and the notes relevant to the timers. 2.3.1 memory map fig. 2.3.1 memory map of registers relevant to timers 2.3.2 relevant registers fig. 2.3.2 structure of prescaler 12, prescaler x, prescaler y 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) 003c 16 003e 16 interrupt control register 1 (icon1) 0027 16 timer y (ty) prescaler y (prey) 003d 16 003f 16 interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 2 (icon2) 002f 16 port control register 2 (pctl2) prescaler 12, prescaler x, prescaler y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 1 1 prescaler 12 (pre12) [address : 20 16 ] prescaler x (prex) [address : 24 16 ] prescaler y (prey) [address : 26 16 ] set a count value of each prescaler. the value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time. when this register is read out, the count value of the corres- ponding prescaler is read out.
3886 group user s manual application 2-25 2.3 timer fig. 2.3.3 structure of timer 1 fig. 2.3.4 structure of timer 2, timer x, timer y timer 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 0 0 0 0 0 0 0 timer 1 (t1) [address : 21 16 ] set a count value of timer 1. the value set in this register is written to both timer 1 and timer 1 latch at the same time. when this register is read out, the timer 1 s count value is read out. timer 2, timer x, timer y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 1 1 timer 2 (t2) [address : 22 16 ] timer x (tx) [address : 25 16 ] timer y (ty) [address : 27 16 ] set a count value of each timer. the value set in this register is written to both each timer and each timer latch at the same time. when this register is read out, each timer s count value is read out.
3886 group user s manual application 2.3 timer fig. 2.3.5 structure of timer xy mode register timer x /timer y operation modes timer mode pulse output mode event counter mode pulse width measurement mode cntr 0 / cntr 1 active edge selection bit (bits 2, 6 of address 23 16 ) contents 0 cntr 0 / cntr 1 interrupt request occurrence: falling edge ; no influence to timer count 1 cntr 0 / cntr 1 interrupt request occurrence: rising edge ; no influence to timer count 0 pulse output start: beginning at h level cntr 0 / cntr 1 interrupt request occurrence: falling edge 1 pulse output start: beginning at l level cntr 0 / cntr 1 interrupt request occurrence: rising edge 0 timer x / timer y: rising edge count cntr 0 / cntr 1 interrupt request occurrence: falling edge 1 timer x / timer y: falling edge count cntr 0 / cntr 1 interrupt request occurrence: rising edge 0 timer x / timer y: h level width measurement cntr 0 / cntr 1 interrupt request occurrence: falling edge 1 timer x / timer y: l level width measurement cntr 0 / cntr 1 interrupt request occurrence: rising edge table 2.3.1 cntr 0 /cntr 1 active edge selection bit function b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 3 4 5 6 7 name 0 0 0 0 timer xy mode register (tm) [address : 23 ] timer xy mode register 0 0 0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b1 b0 1 0 timer x operating mode bits cntr 0 active edge selection bit the function depends on the operating mode of timer x. (refer to table 2.2.1) timer x count stop bit 0 : count start 1 : count stop 16 timer y operating mode bits 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b5 b4 the function depends on the operating mode of timer y. (refer to table 2.2.1) 0 : count start 1 : count stop cntr 1 active edge selection bit timer y count stop bit
3886 group user s manual application 2-27 2.3 timer fig. 2.3.6 structure of port control register 2 port control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 port control register 2 (pctl2) [address 2f 16 ] port output p4 2 /p4 3 clear function selection bit p4 input level selection bit (p4 2 p4 6 ) 0: automatic set 01 16 to timer 1 and ff 16 to prescaler 12 1: no automatic set p8 function selection bit 0: cmos level input 1: ttl level input p7 input level selection bit (p7 0 p7 5 ) p4 output structure selection bit (p4 2 , p4 3 , p4 4 , p4 6 ) int 2 , int 3 , int 4 interrupt switch bit timer y count source selection bit oscillation stabilizing time set after stp instruction released bit 0: cmos level input 1: ttl level input 0: cmos 1: n-channel open-drain 0: port p8/port p8 direction register 1: port p4 input register/port p7 input register 0: int 20 , int 30 , int 40 interrupt 1: int 21 , int 31 , int 41 interrupt 0: f(x in )/16 (f(x cin )/16 in low- speed mode) 1: f(x cin ) 0: only software clear 1: software clear and output data bus buffer 0 reading (system bus side)
3886 group user s manual application 2.3 timer fig. 2.3.7 structure of interrupt request register 1 fig. 2.3.8 structure of interrupt request register 2 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 1 (ireq1) [address : 3c 16 ] int 0 /input buffer full interrupt request bit int 1 /output buffer empty interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued timer y interrupt request bit timer 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued serial i/o1 receive interrupt request bit serial i/o1 transmit/s cl , s da interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? timer 2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ? interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . ? cntr 0 /s cl , s da interrupt request bit cntr 1 /key-on wake-up interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued int 4 interrupt request bit ad converter/key-on wake-up interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued serial i/o2/i 2 c interrupt request bit int 2 /i 2 c interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued int 3 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ?
3886 group user s manual application 2-29 2.3 timer fig. 2.3.9 structure of interrupt control register 1 fig. 2.3.10 structure of interrupt control register 2 interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] int 0 /input buffer full interrupt enable bit int 1 /output buffer empty interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer y interrupt enable bit timer 1 interrupt enable bit serial i/o1 receive interrupt enable bit serial i/o1 transmit/s cl , s da interrupt enable bit timer x interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled i n t e r r u p t c o n t r o l r e g i s t e r 2 b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] f i x t h i s b i t t o 0 . cntr 0 /s cl , s da interrupt enable bit cntr 1 /key-on wake-up interrupt enable bit 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d int 4 interrupt enable bit ad converter/key-on wake-up interrupt enable bit serial i/o2/i 2 c interrupt enable bit int 2 /i 2 c interrupt enable bit int 3 interrupt enable bit 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0
3886 group user s manual application 2.3 timer 2.3.3 timer application examples (1) basic functions and uses [function 1] control of event interval (timer x, timer y, timer 1, timer 2) when a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. generation of an output signal timing generation of a wait time [function 2] control of cyclic operation (timer x, timer y, timer 1, timer 2) the value of the timer latch is automatically written to the corresponding timer each time the timer underflows, and each timer interrupt request occurs in cycles. generation of cyclic interrupts clock function (measurement of 250 ms); see application example 1 control of a main routine cycle [function 3] output of rectangular waveform (timer x, timer y) the output level of the cntr 0 pin or cntr 1 pin is inverted each time the timer underflows (in the pulse output mode). piezoelectric buzzer output; see application example 2 generation of the remote control carrier waveforms [function 4] count of external pulses (timer x, timer y) external pulses input to the cntr 0 pin or cntr 1 pin are counted as the timer count source (in the event counter mode). frequency measurement; see application example 3 division of external pulses generation of interrupts due to a cycle using external pulses as the count source; count of a reel pulse [function 5] measurement of external pulse width (timer x, timer y) the h or l level width of external pulses input to cntr 0 pin or cntr 1 pin is measured (in the pulse width measurement mode). measurement of external pulse frequency (measurement of pulse width of fg pulse ? for a motor); see application example 4 measurement of external pulse duty (when the frequency is fixed) fg pulse ? : pulse used for detecting the motor speed to control the motor speed.
3886 group user s manual application 2-31 2.3 timer tm 0 0 1 prex 255 tx 255 b0 b7 b0 b7 b0 b7 timer xy mode register (address 23 16 ) timer x operating mode: timer mode timer x count: stop clear to 0 when starting count. prescaler x (address 24 16 ) timer x (address 25 16 ) set division ratio 1 icon1 timer x interrupt: enabled 1 b0 b7 interrupt control register 1 (address 3e 16 ) ireq1 b0 b7 interrupt request register 1 (address 3c 16 ) timer x interrupt request (becomes 1 at 250 ms intervals) 0 fig. 2.3.12 relevant registers setting (2) timer application example 1: clock function (measurement of 250 ms) outline : the input clock is divided by the timer so that the clock can count up at 250 ms intervals. specifications : the clock f(x in ) = 4.19 mhz (2 22 hz) is divided by the timer. the clock is counted up in the process routine of the timer x interrupt which occurs at 250 ms intervals. figure 2.3.11 shows the timers connection and setting of division ratios; figure 2.3.12 shows the relevant registers setting; figure 2.3.13 shows the control procedure. fig. 2.3.11 timers connection and setting of division ratios f(x in ) = 4.19 mhz 250 ms 1/16 1/256 1/256 1/4 1 second dividing by 4 with software fixed prescaler x timer x timer x interrupt request bit 0 or 1 0 : no interrupt request issued 1 : interrupt request issued
3886 group user s manual application 2.3 timer fig. 2.3.13 control procedure (address 23 16 ) (address 3c 16 ) (address 3e 16 ), bit4 reset initialization sei tm ireq1 icon1 prex tx tm cli 1 ..... ..... ..... 256 1 256 1 main processing tm prex tx ireq1 tm ..... 1 256 1 256 1 0 0 clock stop ? n y rti (address 23 16 ), bit3 (address 24 16 ) (address 25 16 ) (address 3c 16 ), bit4 (address 23 16 ), bit3 clt ( note 2 ) cld ( note 3 ) push registers to stack (address 24 16 ) (address 25 16 ) (address 23 16 ), bit3 0 ..... ( note 1 ) timer x interrupt process routine clock count up (1/4 second to year) pop registers xxxx1x00 2 all interrupts disabled timer x operating mode : timer mode timer x interrupt request bit cleared timer x interrupt enabled division ratio 1 set to prescaler x and timer x timer x count start interrupts enabled timer x count stop timer reset to restart count from 0 second after completion of clock set timer x count start note 2 : when using index x mode flag (t) note 3 : when using decimal mode flag (d) push registers used in interrupt process routine judgment whether clock stops clock counted up pop registers pushed to stack x: this bit is not used here. set it to 0 or 1 arbitrarily. xxx0xxxx 2 note 1 : perform procedure for completion of clock set only when completing clock set.
3886 group user? manual application 2-33 2.3 timer (3) timer application example 2: piezoelectric buzzer output outline : the rectangular waveform output function of the timer is applied for a piezoelectric buzzer output. specifications : ?he rectangular waveform, dividing the clock f(x in ) = 4.19 mhz (2 22 hz) into about 2 khz (2048 hz), is output from the p5 4 /cntr 0 pin. ?he level of the p5 4 /cntr 0 pin is fixed to ??while a piezoelectric buzzer output stops. figure 2.3.14 shows a peripheral circuit example, and figure 2.3.15 shows the timers connection and setting of division ratios. figures 2.3.16 shows the relevant registers setting, and figure 2.3.17 shows the control procedure. fig. 2.3.14 peripheral circuit example fig. 2.3.15 timers connection and setting of division ratios 3886 group p5 4 /cntr 0 pipipi..... 244 s cntr 0 output the h level is output while a piezoelectric buzzer output stops. 244 s set a division ratio so that the underflow output period of the timer x can be 244 s. 1/16 1/64 1/2 cntr 0 1 f(x in ) = 4.19 mhz fixed prescaler x timer x fixed
3886 group user s manual application 2.3 timer fig. 2.3.16 relevant registers setting fig. 2.3.17 control procedure tm tx 63 1 0 0 1 prex 0 b0 b7 b0 b7 b0 b7 timer xy mode register (address 23 16 ) timer x operating mode: pulse output mode timer x count: stop clear to 0 when starting count. prescaler x (address 24 16 ) timer x (address 25 16 ) set division ratio 1 . cntr 0 active edge selection: output starting at h level reset p5 p5d icon1 tm tx prex 1 ..... ..... ..... 0 xxxx 1001 2 64 1 1 1 ..... output unit tm (address 23 16 ), bit3 0 (address 0a 16 ), bit4 (address 0b 16 ) (address 3e 16 ), bit4 (address 23 16 ) (address 25 16 ) (address 24 16 ) tm (address 23 16 ), bit3 1 tx (address 25 16 ) 64 1 initialization x: this bit is not used here. set it to 0 or 1 arbitrarily. xxx 1 xxxx2 main processing piezoelectric buzzer request ? yes piezoelectric buzzer output start stop piezoelectric buzzer output no timer x interrupt disabled cntr 0 output stop; piezoelectric buzzer output stop division ratio 1 set to timer x and prescaler x processing piezoelectric buzzer request, generated during main processing, in output unit
3886 group user s manual application 2-35 2.3 timer (4) timer application example 3: frequency measurement outline : the following two values are compared to judge whether the frequency is within a valid range. a value by counting pulses input to p5 5 /cntr 1 pin with the timer. a reference value specifications : the pulse is input to the p5 5 /cntr 1 pin and counted by the timer y. a count value is read out at about 2 ms intervals, the timer 1 interrupt interval. when the count value is 28 to 40, it is judged that the input pulse is valid. because the timer is a down-counter, the count value is compared with 227 to 215 (note). note : 227 to 215 = {255 (initial value of counter) 28} to {255 40}; 28 to 40 means the number of valid value. figure 2.3.18 shows the judgment method of valid/invalid of input pulses; figure 2.3.19 shows the relevant registers setting; figure 2.3.20 shows the control procedure. fig. 2.3.18 judgment method of valid/invalid of input pulses input pulse 2 ms 71.4 s = 28 counts ...... 71.4 s or more (14 khz or less) 71.4 s (14 khz) 50 s (20 khz) 50 s or less (20 khz or more) invalid valid invalid 2 ms 50 s = 40 counts ...... ......
3886 group user s manual application 2.3 timer fig. 2.3.19 relevant registers setting tm pre12 63 t1 10 1 1 prey ty 7 0 255 icon1 0 ireq1 0 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 timer y interrupt: disabled timer 1 interrupt: enabled timer xy mode register (address 23 16 ) timer y operating mode: event counter mode timer y count: stop clear to 0 when starting count. prescaler 12 (address 20 16 ) timer y (address 27 16 ) set division ratio 1 . interrupt control register 1 (address 3e 16 ) cntr 1 active edge selection: falling edge count prescaler y (address 26 16 ) timer 1 (address 21 16 ) interrupt request register 1 (address 3c 16 ) judge timer y interrupt request bit. ( 1 of this bit when reading the count value indicates the 256 or more pulses input in the condition of timer y = 255) set 255 just before counting pulses. (after a certain time has passed, the number of input pulses is decreased from this value.) 1
3886 group user s manual application 2-37 2.3 timer fig. 2.3.20 control procedure (address 23 16 ) (address 20 16 ) (address 21 16 ) (address 26 16 ) (address 27 16 ) (address 3e 16 ), bit6 reset sei tm pre12 t1 prey ty icon1 tm cli ..... ..... 0 ireq1(address 3c 16 ), bit5 ? 0 1 rti ..... ty (address 27 16 ) (a) 214 < (a) < 228 0 fpulse 1 fpulse ty (address 27 16 ) ireq1 (address 3c 16 ), bit5 256 1 0 (address 23 16 ), bit7 x: this bit is not used here. set it to 0 or 1 arbitrary. all interrupts disabled timer y operating mode : event counter mode (count a falling edge of pulses input from cntr 1 pin.) division ratio set so that timer 1 interrupt will occur at 2 ms intervals. timer y count start interrupts enabled note 1 : when using index x mode flag (t) note 2 : when using decimal mode flag (d) push registers used in interrupt process routine pop registers pushed to stack counter value initialized timer y interrupt request bit cleared initialization 1110 xxxx2 64 1 8 1 1 1 256 1 1 timer 1 interrupt enabled timer 1 interrupt process routine clt ( note 1 ) cld ( note 2 ) push registers to stack processing as out of range when the count value is 256 or more count value read count value into accumulator (a) stored in range out of range read value with reference value compared comparison result to flag fpulse stored process judgment result pop registers
3886 group user s manual application 2.3 timer (5) timer application example 4: measurement of fg pulse width for motor outline : the timer x counts the h level width of the pulses input to the p5 4 /cntr 0 pin. an underflow is detected by the timer x interrupt and an end of the input pulse h level is detected by the cntr 0 interrupt. specifications : the timer x counts the h level width of the fg pulse input to the p5 4 /cntr 0 pin. when the clock frequency is 4.19 mhz, the count source is 3.8 s, which is obtained by dividing the clock frequency by 16. measurement can be performed to 250 ms in the range of ffff 16 to 0000 16 . figure 2.3.21 shows the timers connection and setting of division ratio; figure 2.3.22 shows the relevant registers setting; figure 2.3.23 shows the control procedure. fig. 2.3.21 timers connection and setting of division ratios 250 ms 1/16 1/256 1/256 f(x in ) = 4.19 mhz fixed prescaler x timer x timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 or 1
3886 group user s manual application 2-39 2.3 timer fig. 2.3.22 relevant registers setting tm prex 255 tx 01 1 1 255 icon1 ireq1 1 0 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 timer x interrupt: enabled timer xy mode register (address 23 16 ) timer x operating mode: pulse width measurement mode timer x count: stop clear to 0 when starting count. prescaler x (address 24 16 ) timer x (address 25 16 ) set division ratio 1 . interrupt control register 1 (address 3e 16 ) cntr 0 active edge selection: h level width measurement cntr 0 interrupt: enabled interrupt request register 1 (address 3c 16 ) timer x interrupt request (set to 1 automatically when timer x underflows) icon2 1 b0 b7 interrupt control register 2 (address 3f 16 ) ireq2 0 b0 b7 interrupt request register 2 (address 3d 16 ) cntr 0 interrupt request (set to 1 automatically when h level input came to the end)
3886 group user s manual application 2.3 timer fig. 2.3.23 control procedure (address 23 16 ) (address 24 16 ) (address 25 16 ) (address 3c 16 ), bit4 (address 3e 16 ), bit4 (address 3d 16 ), bit0 (address 3f 16 ), bit0 reset sei tm prex tx ireq1 icon1 ireq2 icon2 tm cli ..... ..... 0 ..... rti rti prex inverted (a) (a) low-order 8-bit result of pulse width measurement (a) high-order 8-bit result of pulse width measurement prex (address 24 16 ) tx (address 25 16 ) (address 23 16 ), bit3 256 1 256 1 0 1 0 1 xxxx 1011 2 tx inverted (a) 256 1 256 1 all interrupts disabled timer x operating mode : pulse width measurement mode (measure h level of pulses input from cntr 0 pin.) set division ratio so that timer x interrupt will occur at 250 ms intervals. timer x interrupt request bit cleared timer x interrupt enabled cntr 0 interrupt request bit cleared cntr 0 interrupt enabled timer x count start interrupts enabled note 1 : when using index x mode flag (t) note 2 : when using decimal mode flag (d) push registers used in interrupt process routine pop registers pushed to stack pop registers initialization timer x interrupt process routine clt ( note 1 ) cld ( note 2 ) push registers to stack process errors error occurs cntr 0 interrupt process routine division ratio set so that timer x interrupt will occur at 250 ms intervals. read the count value and store it to ram l x: this bit is not used here. set it to 0 or 1 arbitrarily.
3886 group user s manual application 2-41 2.3 timer 2.3.4 notes on timer if a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). when switching the count source by the timer y count source selection bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. therefore, select the timer count source before set the value to the prescaler and the timer.
3886 group user? manual application 2.4 serial i/o 2.4 serial i/o this paragraph explains the registers setting method and the notes relevant to the serial i/o. 2.4.1 memory map fig. 2.4.1 memory map of registers relevant to serial i/o 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 transmit/receive buffer register (tb/rb) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) 003e 16 0 0 3 c 1 6 interrupt request register 1 (ireq1) interrupt control register 1 (icon1) ~ ~ ~ ~ ~ ~ ~ ~ 0 0 3 a 1 6 interrupt edge selection register (intedge) 0 0 1 d 1 6 serial i/o2 control register (sio2con) 0 0 1 f 1 6 serial i/o2 register (sio2) 0039 16 interrupt source selection register (intsel) 0 0 3 f 1 6 003d 16 interrupt request register 2 (ireq2) interrupt control register 2 (icon2)
3886 group user s manual application 2-43 2.4 serial i/o fig. 2.4.3 structure of serial i/o status register fig. 2.4.2 structure of transmit/receive buffer register 2.4.2 relevant registers t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e ? ? ? ? ? ? ? ? t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r ( t b / r b ) [ a d d r e s s : 1 8 1 6 ] t h e t r a n s m i s s i o n d a t a i s w r i t t e n t o o r t h e r e c e i v e d a t a i s r e a d o u t f r o m t h i s b u f f e r r e g i s t e r . a t w r i t i n g : a d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r . a t r e a d i n g : t h e c o n t e n t s o f t h e r e c e i v e b u f f e r r e g i s t e r a r e r e a d o u t . n o t e : t h e c o n t e n t s o f t r a n s m i t b u f f e r r e g i s t e r c a n n o t b e r e a d o u t . t h e d a t a c a n n o t b e w r i t t e n t o t h e r e c e i v e b u f f e r r e g i s t e r . s e r i a l i / o 1 s t a t u s r e g i s t e r b 7b 6b5b 4b 3b 2b 1b 0 b function a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 1 serial i/o1 status register (sio1sts) [address : 19 16 ] n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 1 . ? ? ? ? ? ? ? ? t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 o v e r r u n e r r o r f l a g ( o e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) p a r i t y e r r o r f l a g ( p e ) f r a m i n g e r r o r f l a g ( f e ) s u m m i n g e r r o r f l a g ( s e ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d 0 : n o e r r o r 1 : o v e r r u n e r r o r 0 : n o e r r o r 1 : p a r i t y e r r o r 0 : n o e r r o r 1 : f r a m i n g e r r o r
3886 group user s manual application 2.4 serial i/o fig. 2.4.5 structure of uart control register fig. 2.4.4 structure of serial i/o1 control register serial i/o1 control register b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) [ a d d r e s s : 1 a 1 6 ] 0 : f ( x i n ) ( f ( x c i n ) i n l o w s p e e d m o d e ) 1 : f ( x i n ) / 4 ( f ( x c i n ) / 4 i n l o w s p e e d m o d e ) b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) t r a n s m i t e n a b l e b i t ( t e ) r e c e i v e e n a b l e b i t ( r e ) s e r i a l i / o 1 e n a b l e b i t ( s i o e ) s rdy1 output enable bit (srdy) 0 : p 4 7 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 4 7 p i n o p e r a t e s a s s r d y 1 o u t p u t p i n 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) i n c l o c k s y n c h r o n o u s s e r i a l i / o 0 : b r g o u t p u t d i v i d e d b y 4 1 : e x t e r n a l c l o c k i n p u t i n u a r t 0 : b r g o u t p u t d i v i d e d b y 1 6 1 : e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 s e r i a l i / o 1 m o d e s e l e c t i o n b i t ( s i o m ) 0 : c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o 1 : c l o c k s y n c h r o n o u s s e r i a l i / o 0 : s e r i a l i / o 1 d i s a b l e d ( p i n s p 4 4 t o p 4 7 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o 1 e n a b l e d ( p i n s p 4 4 t o p 4 7 o p e r a t e a s s e r i a l i / o p i n s ) b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 1 uart control register (uartcon) [address : 1b 16 ] n o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . t h e s e a r e w r i t e d i s a b l e d b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 1 . ? ? ? u a r t c o n t r o l r e g i s t e r c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) p a r i t y e n a b l e b i t ( p a r e ) s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) parity selection bit (pars) in output mode 0 : cmos output 1 : n-channel open-drain output 0 : 8 bits 1 : 7 bits 0 : parity checking disabled 1 : parity checking enabled 0 : 1 stop bit 1 : 2 stop bits 0 : even parity 1 : odd parity p4 5 /txd p-channel output disable bit (poff) 1 1 0
3886 group user s manual application 2-45 2.4 serial i/o fig. 2.4.6 structure of baud rate generator fig. 2.4.7 structure of serial i/o2 control register baud rate generator b 7b 6b 5b 4b3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? baud rate generator (brg) [address : 1c 16 ] set a count value of baud rate generator. b 7b 6b 5b 4b3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 serial i/o2 control register (sio2con) [address : 1d 16 ] s e r i a l i / o 2 c o n t r o l r e g i s t e r 0 0 0 0 : f ( x i n ) / 8 0 0 1 : f ( x i n ) / 1 6 0 1 0 : f ( x i n ) / 3 2 0 1 1 : f ( x i n ) / 6 4 1 1 0 : f ( x i n ) / 1 2 8 1 1 1 : f ( x i n ) / 2 5 6 internal synchronous clock selection bits b 2 b 1 b 0 serial i/o2 port selection bit 0: i/o port (p7 1 , p7 2 ) 1: s out2 ,s clk2 signal output 0 s rdy2 output enable bit 0: i/o port (p7 3 ) 1: s rdy2 signal output transfer direction selection bit 0: lsb first 1: msb first serial i/o2 synchronous clock selection bit 0: external clock 1: internal clock comparator reference input selection bit 0: p0 0 /p3 ref input 1: reference input fixed
3886 group user s manual application 2.4 serial i/o fig. 2.4.8 structure of serial i/o2 register fig. 2.4.9 structure of interrupt source selection register serial i/o2 register b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e ? ? ? ? ? ? ? ? s e r i a l i / o 2 r e g i s t e r ( s i o 2 ) [ a d d r e s s : 1 f 1 6 ] serial i/o2 register is the shift register for serial transfer. at transmit: transmit data is set. at receive: receive data is set. interrupt source selection register b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t s o u r c e s e l e c t i o n b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 0 i n t e r r u p t 1 : i n p u t b u f f e r f u l l i n t e r r u p t int 2 /i 2 c interrupt source selection bit cntr 1 /key-on wake-up interrupt source selection bit 0 : int 1 interrupt 1 : output buffer empty interrupt s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t c n t r 0 / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : s e r i a l i / o 1 t r a n s m i t i n t e r r u p t 1 : s c l , s d a i n t e r r u p t 0 : c n t r 0 i n t e r r u p t 1 : s c l , s d a i n t e r r u p t s e r i a l i / o 2 / i 2 c i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : serial i/o2 interrupt 1 : i 2 c interrupt 0 : int 2 interrupt 1 : i 2 c interrupt 0 : c n t r 1 i n t e r r u p t 1 : k e y - o n w a k e - u p i n t e r r u p t a d c o n v e r t e r / k e y - o n w a k e - u p i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : a - d c o n v e r t e r i n t e r r u p t 1 : k e y - o n w a k e - u p i n t e r r u p t ? 1 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 2 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 3 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . interrupt source selection register [intsel: address 0039 16 ] ? 1 ? 2 ? 2 ? 3 ? 3 ? 1
3886 group user s manual application 2-47 2.4 serial i/o fig. 2.4.10 structure of interrupt edge selection register interrupt edge selection register b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) [ a d d r e s s : 3 a 1 6 ] n o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . t h e s e a r e w r i t e d i s a b l e d b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active i n t 3 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 2 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active ? ? ? n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . i n t 4 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : falling edge active 1 : rising edge active
3886 group user s manual application 2.4 serial i/o fig. 2.4.11 structure of interrupt request register 1 fig. 2.4.12 structure of interrupt request register 2 interrupt request register 1 b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s : 3 c 1 6 ] i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t r e q u e s t b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued timer y interrupt request bit timer 1 interrupt request bit ? : t h e s e b i t s c a n b e c l e a r e d t o 0 b y p r o g r a m , b u t c a n n o t b e s e t t o 1 . 0 : no interrupt request issued 1 : interrupt request issued s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued t i m e r x i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? t i m e r 2 i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued ? interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . ? c n t r 0 / s c l , s d a i n t e r r u p t r e q u e s t b i t cntr 1 /key-on wake-up interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued int 4 interrupt request bit a d c o n v e r t e r / k e y - o n w a k e - u p i n t e r r u p t r e q u e s t b i t ? : t h e s e b i t s c a n b e c l e a r e d t o 0 b y p r o g r a m , b u t c a n n o t b e s e t t o 1 . 0 : no interrupt request issued 1 : interrupt request issued s e r i a l i / o 2 / i 2 c i n t e r r u p t r e q u e s t b i t i n t 2 / i 2 c i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued i n t 3 i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ?
3886 group user s manual application 2-49 2.4 serial i/o fig. 2.4.13 structure of interrupt control register 1 fig. 2.4.14 structure of interrupt control register 2 interrupt control register 1 b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s : 3 e 1 6 ] i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t e n a b l e b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled timer y interrupt enable bit timer 1 interrupt enable bit s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled t i m e r 2 i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] f i x t h i s b i t t o 0 . c n t r 0 / s c l , s d a i n t e r r u p t e n a b l e b i t cntr 1 /key-on wake-up interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled int 4 interrupt enable bit ad converter/key-on wake-up interrupt enable bit serial i/o2/i 2 c interrupt enable bit i n t 2 / i 2 c i n t e r r u p t e n a b l e b i t i n t 3 i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0
3886 group user s manual application 2.4 serial i/o 2.4.3 serial i/o connection examples (1) control of peripheral ic equipped with cs pin figure 2.4.15 shows connection examples of a peripheral ic equipped with the cs pin. there are connection examples using a clock synchronous serial i/o mode. fig. 2.4.15 serial i/o connection examples (1) por t s cl k t x d r x d por t cs clk in out c s c l k i n o u t (4) connection of plural ic 3886 group p e r i p h e r a l i c 1 p e r i p h e r a l i c 2 p o r t s c l k t x d c s c l k i n o u t ( 2 ) t r a n s m i s s i o n a n d r e c e p t i o n 3 8 8 6 g r o u p p e r i p h e r a l i c ( e p r o m e t c . ) 2 ( 3 ) t r a n s m i s s i o n a n d r e c e p t i o n ( w h e n c o n n e c t i n g r x d w i t h t x d ) ( w h e n c o n n e c t i n g i n w i t h o u t i n p e r i p h e r a l i c ) cs clk in out 3 8 8 6 g r o u p peripheral ic (e prom etc.) 2 ? 2 p o r t m e a n s a n o u t p u t p o r t c o n t r o l l e d b y s o f t w a r e . w h e n s e r i a l i / o 2 i s u s e d , s o u t a n d s i n a r e u s e d , n o t t x d a n d r x d . n o t e s 1 : 2 : p o r t s c l k t x d c s c l k d a t a ( 1 ) o n l y t r a n s m i s s i o n ( u s i n g t h e r x d p i n a s a n i / o p o r t ) 3 8 8 6 g r o u p p e r i p h e r a l i c ( o s d c o n t r o l l e r e t c . ) ? 1 ? 1 : s e l e c t a n n - c h a n n e l o p e n - d r a i n o u t p u t f o r t x d p i n o u t p u t c o n t r o l . ? 2 : u s e t h e o u t p i n o f p e r i p h e r a l i c w h i c h i s a n n - c h a n n e l o p e n - d r a i n o u t p u t a n d b e c o m e s h i g h i m p e d a n c e d u r i n g r e c e i v i n g d a t a . por t s cl k t x d r x d r x d
3886 group user s manual application 2-51 2.4 serial i/o (2) connection with microcomputer figure 2.4.16 shows connection examples with another microcomputer. fig. 2.4.16 serial i/o connection examples (2) (4) in uart s cl k t x d r x d clk in out (2) selecting external cloc k 3886 grou p microcomputer ( 3 ) u s i n g s r d y s i g n a l o u t p u t f u n c t i o n ( s e l e c t i n g a n e x t e r n a l c l o c k ) s rd y s cl k t x d r x d rdy clk in out 3886 grou p m i c r o c o m p u t e r clk in out ( 1 ) s e l e c t i n g i n t e r n a l c l o c k 3 8 8 6 g r o u p m i c r o c o m p u t e r r x d t x d s c l k t x d r x d r x d t x d 3886 grou p microcomputer ? ? . w h e n s e r i a l i / o 2 i s u s e d , u a r t c a n n o t b e u s e d . n o t e : w h e n s e r i a l i / o 2 i s u s e d , s o u t a n d s i n a r e u s e d , n o t t x d a n d r x d .
3886 group user s manual application 2.4 serial i/o 2.4.4 setting of serial i/o transfer data format a clock synchronous or clock asynchronous (uart) can be selected as a data format of serial i/o1. a clock synchronous is used as a data format of serial i/o2. figure 2.4.17 shows the serial i/o transfer data format. fig. 2.4.17 serial i/o transfer data format 1 s t - 8 d a t a - 1 s p s t lsb serial i/o1 u a r t clock synchronous serial i/o 1 s t - 7 d a t a - 1 s p s t lsb 1 s t - 8 d a t a - 1 p a r - 1 s p s t lsb 1 s t - 7 d a t a - 1 p a r - 1 s p s t lsb 1 s t - 8 d a t a - 2 s p s t lsb 1st-7data-2sp s t lsb 1st-8data-1par-2sp st lsb 1 s t - 7 d a t a - 1 p a r - 2 s p st lsb msb s p msb s p m s b p a r s p msb p a r s p m s b 2 s p m s b 2 s p msb par 2 sp msb par 2 sp l s b f i r s t st : start bit sp : stop bit par : parity bit serial i/o2 c l o c k s y n c h r o n o u s s e r i a l i / o l s b f i r s t msb first
3886 group user s manual application 2-53 2.4 serial i/o 2.4.5 serial i/o application examples (1) communication using clock synchronous serial i/o (transmit/receive) outline : 2-byte data is transmitted and received, using the clock synchronous serial i/o. the s rdy1 signal is used for communication control. figure 2.4.18 shows a connection diagram, and figure 2.4.19 shows a timing chart. figure 2.4.20 shows a registers setting relevant to the transmitting side, and figure 2.4.21 shows registers setting relevant to the receiving side. fig. 2.4.18 connection diagram specifications : the serial i/o1 is used (clock synchronous serial i/o is selected.) synchronous clock frequency : 125 khz (f(x in ) = 4 mhz is divided by 32) the s rdy1 (receivable signal) is used. the receiving side outputs the s rdy1 signal at intervals of 2 ms (generated by timer), and 2-byte data is transferred from the transmitting side to the receiving side. fig. 2.4.19 timing chart p4 2 / int 0 s clk1 t x d 3 8 8 6 g r o u p s r d y 1 s c l k 1 r x d 3886 grou p transmitting side r e c e i v i n g s i d e d 0 d 4 d 2 d 1 d 6 d 5 d 7 d 3 d 0 d 4 d 2 d 1 d 6 d 5 d 7 d 3 d 0 d 1 t x d s c l k 1 s r d y 1 2 ms
3886 group user s manual application 2.4 serial i/o fig. 2.4.20 registers setting relevant to transmitting side s e r i a l i / o 1 s t a t u s r e g i s t e r ( a d d r e s s : 1 9 1 6 ) s i o 1 s t s transmit buffer empty flag confirm that the data has been transferred from transmit buffer register to transmit shift register. when this flag is 1 , it is possible to write the next transmission data in to transmit buffer register. t r a n s m i t t i n g s i d e transmit shift register shift completion flag confirm completion of transmitting 1-byte data with this flag. 1 : transmit shift completed b 7 b 0 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( a d d r e s s : 3 a 1 6 ) i n t e d g e int 0 interrupt edge selection bit : falling edge active b 7 b 0 baud rate generator (address : 1c 16 ) brg set division ratio 1 . 7 b 7 b 0 serial i/o1 control register (address : 1a 16 ) s i o 1 c o n brg counter source selection bit : f(x in ) serial i/o1 synchronous clock selection bit : brg/4 transmit enable bit : transmit enabled receive enable bit : receive disabled serial i/o1 mode selection bit : clock synchronous serial i/o serial i/o1 enable bit : serial i/o1 enabled b 7 b 0 0 0 0 11 1 0
3886 group user s manual application 2-55 2.4 serial i/o fig. 2.4.21 registers setting relevant to receiving side b 7 b 0 receiving side serial i/o1 control register (address : 1a 16 ) s i o 1 c o n serial i/o1 synchronous clock selection bit : external clock s rdy1 output enable bit : s rdy1 output enabled transmit enable bit : transmit enabled set this bit to 1 , using s rdy1 output. r e c e i v e e n a b l e b i t : r e c e i v e e n a b l e d s e r i a l i / o 1 m o d e s e l e c t i o n b i t : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 1 e n a b l e b i t : s e r i a l i / o 1 e n a b l e d 1 1 1 1 1 1 s e r i a l i / o 1 s t a t u s r e g i s t e r ( a d d r e s s : 1 9 1 6 ) sio1st s b 7 b 0 receive buffer full flag c o n f i r m c o m p l e t i o n o f r e c e i v i n g 1 - b y t e d a t a w i t h t h i s f l a g . 1 : at completing reception 0 : at reading out contents of receive buffer register overrun error flag 1 : when data is ready in receive shift register while receive buffer register contains the data. parity error flag 1 : when a parity error occurs in enabled parity. framing error flag 1 : when stop bits cannot be detected at the specified timing. summing error flag 1 : when any one of the following errors occurs. overrun error parity error framing error
3886 group user s manual application 2.4 serial i/o figure 2.4.22 shows a control procedure of the transmitting side, and figure 2.4.23 shows a control procedure of the receiving side. fig. 2.4.22 control procedure of transmitting side r e s e t i n i t i a l i z a t i o n ( a d d r e s s : 1 a 1 6 ) ( a d d r e s s : 1 c 1 6 ) ( a d d r e s s : 3 a 1 6 ) , b i t 0 s i o 1 c o n b r g i n t e d g e 8 1 0 . . . . . tb/rb (address : 18 16 ) the first byte of a transmission data t r a n s m i s s i o n d a t a w r i t e t r a n s m i t b u f f e r e m p t y f l a g i s s e t t o 0 b y t h i s w r i t i n g . d e t e c t i o n o f i n t 0 f a l l i n g e d g e i r e q 1 ( a d d r e s s : 3 c 1 6 ) , b i t 0 ? 1 0 j u d g m e n t o f t r a n s f e r r i n g f r o m t r a n s m i t b u f f e r r e g i s t e r t o t r a n s m i t s h i f t r e g i s t e r ( t r a n s m i t b u f f e r e m p t y f l a g ) sio1sts (address : 19 16 ), bit0? 1 0 t b / r b ( a d d r e s s : 1 8 1 6 ) t r a n s m i s s i o n d a t a w r i t e t r a n s m i t b u f f e r e m p t y f l a g i s s e t t o 0 b y t h i s w r i t i n g . t h e s e c o n d b y t e o f a t r a n s m i s s i o n d a t a j u d g m e n t o f t r a n s f e r r i n g f r o m t r a n s m i t b u f f e r r e g i s t e r t o t r a n s m i t s h i f t r e g i s t e r ( t r a n s m i t b u f f e r e m p t y f l a g ) s i o 1 s t s ( a d d r e s s : 1 9 1 6 ) , b i t 0 ? 1 0 j u d g m e n t o f s h i f t c o m p l e t i o n o f t r a n s m i t s h i f t r e g i s t e r ( t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ) sio1sts (address : 19 16 ), bit2 ? 1 0 i r e q 1 ( a d d r e s s : 3 c 1 6 ) , b i t 0 0 1101xx00 2 x: this bit is not used here. set it to 0 or 1 arbitrarily.
3886 group user s manual application 2-57 2.4 serial i/o fig. 2.4.23 control procedure of receiving side pass 2 ms? r e s e t i n i t i a l i z a t i o n s i o 1 c o n ( a d d r e s s : 1 a 1 6 ) 1 1 1 1 x 1 1 x 2 . . . . . t b / r b ( a d d r e s s : 1 8 1 6 ) d u m m y d a t a s rdy1 output s rdy1 signal is output by writing data to the tb/rb. using the s rdy1 , set transmit enable bit (bit4) of the sio1con to 1. an interval of 2 ms generated by timer y n judgment of completion of receiving (receive buffer full flag) sio1sts (address : 19 16 ), bit1? 1 0 r e a d o u t r e c e p t i o n d a t a f r o m t b / r b ( a d d r e s s : 1 8 1 6 ) reception of the first byte data receive buffer full flag is set to 0 by reading data. judgment of completion of receiving (receive buffer full flag) sio1sts (address : 19 16 ), bit1? 1 0 read out reception data from tb/rb (address : 18 16 ) reception of the second byte data. receive buffer full flag is set to 0 by reading data. x : t h i s b i t i s n o t u s e d h e r e . s e t i t t o 0 o r 1 a r b i t r a r i l y .
3886 group user s manual application 2.4 serial i/o (2) output of serial data (control of peripheral ic) outline : 4-byte data is transmitted and received, using the clock synchronous serial i/o. the cs signal is output to a peripheral ic through port p5 3 . the example for using serial i/o1 and the example using for serial i/o2 are shown. the specification of these examples are the same. figure 2.4.24 shows a connection diagram, and figure 2.4.25 shows a timing chart. fig. 2.4.24 connection diagram specifications : the serial i/o is used (clock synchronous serial i/o is selected.) synchronous clock frequency : 125 khz (f(x in ) = 4 mhz is divided by 32) transfer direction : lsb first the serial i/o interrupt is not used. port p5 3 is connected to the cs pin ( l active) of the peripheral ic for transmission control; the output level of port p5 3 is controlled by software. fig. 2.4.25 timing chart p 5 3 s c l k 1 t x d c s p e r i p h e r a l i c 3 8 8 6 g r o u p (1) example for using serial i/o1 data cs cl k cl k d a t a p 5 3 s c l k 2 s o u t 2 c s p e r i p h e r a l i c 3 8 8 6 g r o u p (2) example for using serial i/o2 data c s c l k cl k d a t a cs d o 0 do 1 do 2 d o 3 clk d a t a note: when serial i/o2 is used, s out2 pin is in the high-impedance state after the transfer is completed.
3886 group user s manual application 2-59 2.4 serial i/o figure 2.4.26 shows registers setting relevant to serial i/o1, and figure 2.4.27 shows a setting of serial i/o1 transmission data. fig. 2.4.27 setting of serial i/o1 transmission data fig. 2.4.26 registers setting relevant to serial i/o1 s r d y 1 o u t p u t e n a b l e b i t : s r d y 1 o u t p u t d i s a b l e d s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t : b r g / 4 0 s e r i a l i / o 1 t r a n s m i t i n t e r r u p t e n a b l e b i t : i n t e r r u p t d i s a b l e d icon1 interrupt control register 1 (address : 3e 16 ) s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t b i t c o n f i r m c o m p l e t i o n o f t r a n s m i t t i n g 1 - b y t e d a t a b y o n e u n i t . 1 : t r a n s m i t s h i f t c o m p l e t i o n i r e q 1 interrupt request register 1 (address : 3c 16 ) 00 1 s i o 1 c o n s e r i a l i / o 1 c o n t r o l r e g i s t e r ( a d d r e s s : 1 a 1 6 ) 0 0 11 b r g c o u n t s o u r c e s e l e c t i o n b i t : f ( x i n ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t : t r a n s m i t s h i f t o p e r a t i n g c o m p l e t i o n t r a n s m i t e n a b l e b i t : t r a n s m i t e n a b l e d 1 receive enable bit : receive disabled b 7b 0 0 b 7b 0 b 7b 0 serial i/o1 mode selection bit : clock synchronous serial i/o serial i/o1 enable bit : serial i/o1 enabled 0 p4 5 /t x d p-channel output disable bit : cmos output u a r t c o n u a r t c o n t r o l r e g i s t e r ( a d d r e s s : 1 b 1 6 ) b7 b0 7 set division ratio 1 . b r g b a u d r a t e g e n e r a t o r ( a d d r e s s : 1 c 1 6 ) b 7b 0 set a transmission data. confirm that transmission of the previous data is completed (bit 3 of the interrupt request register 1 is 1 ) before writing data. t b / r b t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r ( a d d r e s s : 1 8 1 6 ) b 7b 0
3886 group user s manual application 2.4 serial i/o when the registers are set as shown in fig. 2.4.26, the serial i/o1 can transmit 1-byte data by writing data to the transmit buffer register. thus, after setting the cs signal to l , write the transmission data to the transmit buffer register by each 1 byte, and return the cs signal to h when the target number of bytes has been transmitted. figure 2.4.28 shows a control procedure of serial i/o1. fig. 2.4.28 control procedure of serial i/o1 p5 (address : 0a 16 ), bit3 0 0 n y 1 i r e q 1 ( a d d r e s s : 3 c 1 6 ) , b i t 3 ? c o m p l e t e t o t r a n s m i t d a t a ? i n i t i a l i z a t i o n s i o 1 c o n u a r t c o n b r g i c o n 1 p 5 p 5 d . . . .. . . . ( a d d r e s s : 1 a 1 6 ) ( a d d r e s s : 1 b 1 6 ) , b i t 4 ( a d d r e s s : 1 c 1 6 ) ( a d d r e s s : 3 e 1 6 ) , b i t 3 ( a d d r e s s : 0 a 1 6 ) , b i t 3 ( a d d r e s s : 0 b 1 6 ) 1 1 0 1 1 0 0 0 2 x x x x 1 x x x 2 ireq1 (address : 3c 16 ), bit3 0 t b / r b ( a d d r e s s : 1 8 1 6 ) p5 (address : 0a 16 ), bit3 1 a transmission data cs signal output level to l set serial i/o1 transmit interrupt request bit set to 0 transmission data write (start of transmit 1-byte data) judgment of completion of transmitting 1-byte data use any of ram area as a counter for counting the number of transmitted bytes judgment of completion of transmitting the target number of bytes return the cs signal output level to h when transmission of the target number of bytes is completed serial i/o1 transmit interrupt : disabled cs signal output port set ( h level output) r e s e t 0 8 1 0 1 x : t h i s b i t i s n o t u s e d h e r e . s e t i t t o 0 o r 1 a r b i t r a r i l y . serial i/o1 set
3886 group user s manual application 2-61 2.4 serial i/o figure 2.4.29 shows registers setting relevant to serial i/o2, and figure 2.4.30 shows a setting of serial i/o2 transmission data. fig. 2.4.30 setting of serial i/o2 transmission data fig. 2.4.29 registers setting relevant to serial i/o2 internal synchronous clock selection bits: f(x in )/32 0 serial i/o2 transmit interrupt enable bit : interrupt disabled i c o n 2 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( a d d r e s s : 3 f 1 6 ) serial i/o2 transmit interrupt request bit confirm completion of transmitting 1-byte data by one unit. 1 : transmit shift completion i r e q 2 interrupt request register 2 (address : 3d 16 ) 01 0 s i o 2 c o n s e r i a l i / o 2 c o n t r o l r e g i s t e r ( a d d r e s s : 1 d 1 6 ) 0 0 11 serial i/o2 port selection bit: serial i/o2 used s rdy2 output enable bit: s rdy2 output not used x t r a n s f e r d i r e c t i o n s e l e c t i o n b i t : l s b f i r s t b 7b0 0 b 7b0 b7 b0 s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t : i n t e r n a l c l o c k set a transmission data. confirm that transmission of the previous data is completed (bit 2 of the interrupt request register 2 is 1 ) before writing data. s i o 2 serial i/o2 register (address : 1f 16 ) b7 b0
3886 group user s manual application 2.4 serial i/o when the registers are set as shown in fig. 2.4.29, the serial i/o2 can transmit 1-byte data by writing data to the serial i/o2 register. thus, after setting the cs signal to l , write the transmission data to serial i/o2 by each 1 byte, and return the cs signal to h when the target number of bytes has been transmitted. figure 2.4.31 shows a control procedure of serial i/o2. fig. 2.4.31 control procedure of serial i/o2 p 5 ( a d d r e s s : 0 a 1 6 ) , b i t 3 0 0 n y 1 i r e q 2 ( a d d r e s s : 3 d 1 6 ) , b i t 2 ? c o m p l e t e t o t r a n s m i t d a t a ? initialization s i o 2 c o n i c o n 2 p 5 p 5 d . . . .. . . . ( a d d r e s s : 1 d 1 6 ) ( a d d r e s s : 3 f 1 6 ) , b i t 2 ( a d d r e s s : 0 a 1 6 ) , b i t 3 ( a d d r e s s : 0 b 1 6 ) 0 1 0 0 1 0 1 0 2 x x x x 1 x x x 2 ireq2 (address : 3d 16 ), bit2 0 s i o 2 ( a d d r e s s : 1 f 1 6 ) p 5 ( a d d r e s s : 0 a 1 6 ) , b i t 3 1 a transmission data serial i/o2 control register set serial i/o2 interrupt request bit set to 0 transmission data write (start of transmit 1-byte data) judgment of completion of transmitting 1 - byte data use any of ram area as a counter fo r counting the number of transmitted bytes judgment of completion of transmittin g the target number of bytes serial i/o2 transmit interrupt : disabled cs signal output port set ( h level output) r e s e t 0 1 x : t h i s b i t i s n o t u s e d h e r e . s e t i t t o 0 o r 1 a r b i t r a r i l y . cs signal output level to l set return the cs signal output level to h when transmission of the target number of bytes is completed
3886 group user s manual application 2-63 2.4 serial i/o (3) cyclic transmission or reception of block data (data of specified number of bytes) between two microcomputers outline : when the clock synchronous serial i/o is used for communication, synchronization of the clock and the data between the transmitting and receiving sides may be lost because of noise included in the synchronous clock. it is necessary to correct that constantly, using heading adjustment . this heading adjustment is carried out by using the interval between blocks in this example. figure 2.4.32 shows a connection diagram. fig. 2.4.32 connection diagram specifications : the serial i/o is used (clock synchronous serial i/o is selected). synchronous clock frequency : 131 khz (f(x in ) = 4.19 mhz is divided by 32) byte cycle: 488 s number of bytes for transmission or reception : 8 byte/block block transfer cycle : 16 ms block transfer term : 3.5 ms interval between blocks : 12.5 ms heading adjustment time : 8 ms limitations of specifications : reading of the reception data and setting of the next transmission data must be completed within the time obtained from byte cycle time for transferring 1-byte data (in this example, the time taken from generating of the serial i/o1 receive interrupt request to input of the next synchronous clock is 431 s). heading adjustment time < interval between blocks must be satisfied. s c l k master unit s clk s l a v e u n i t t x d r x d t x d r x d n o t e : w h e n s e r i a l i / o 2 i s u s e d , s o u t a n d s i n a r e u s e d , n o t t x d a n d r x d .
3886 group user s manual application 2.4 serial i/o the communication is performed according to the timing shown in figure 2.4.33. in the slave unit, when a synchronous clock is not input within a certain time (heading adjustment time), the next clock input is processed as the beginning (heading) of a block. when a clock is input again after one block (8 byte) is received, the clock is ignored. figure 2.4.34 shows relevant registers setting. fig. 2.4.33 timing chart fig. 2.4.34 relevant registers setting d 0 b y t e c y c l e b l o c k t r a n s f e r t e r m block transfer cycle d 1 d 2 d 7 d 0 interval between blocks processing for heading adjustment h e a d i n g a d j u s t m e n t t i m e m a s t e r u n i t transmit enabled s i o 1 c o n s e r i a l i / o 1 c o n t r o l r e g i s t e r ( a d d r e s s : 1 a 1 6 ) synchronous clock : brg/4 transmit interrupt source : transmit shift operating completion r e c e i v e e n a b l e d clock synchronous serial i/o 0 1 1 110 0 1 s e r i a l i / o 1 e n a b l e d brg count source : f(x in ) s r d y 1 o u t p u t d i s a b l e d not affected by external clock transmit enabled sio1con serial i/o1 control register (address : 1a 16 ) n o t u s e t h e s e r i a l i / o 1 t r a n s m i t i n t e r r u p t receive enabled clock synchronous serial i/o 1 1 1 1 s l a v e u n i t 1 serial i/o1 enabled 0 s y n c h r o n o u s c l o c k : e x t e r n a l c l o c k u a r t c o n uart control register (address : 1b 16 ) p 4 5 / t x d p i n : c m o s o u t p u t 0 b o t h o f u n i t s b 7b0 7 b r g b 7b0 baud rate generator (address : 1c 16 ) s e t d i v i s i o n r a t i o 1 . b7 b0 b7 b0 s rdy1 output disabled
3886 group user s manual application 2-65 2.4 serial i/o control procedure : control in the master unit after setting the relevant registers shown in figure 2.4.34, the master unit starts transmission or reception of 1-byte data by writing transmission data to the transmit buffer register. to perform the communication in the timing shown in figure 2.4.33, take the timing into account and write transmission data. additionally, read out the reception data when the serial i/o1 transmit interrupt request bit is set to 1, or before the next transmission data is written to the transmit buffer register. figure 2.4.35 shows a control procedure of the master unit using timer interrupts. fig. 2.4.35 control procedure of master unit i n t e r r u p t p r o c e s s i n g r o u t i n e e x e c u t e d e v e r y 4 8 8 s write a transmission data read a reception data n w i t h i n a b l o c k t r a n s f e r t e r m ? y y c o m p l e t e t o t r a n s f e r a b l o c k ? n r t i write the first transmission data (first byte) in a block count a block interval counter n start a block transfer? y generation of a certain block interval by using a timer or other functions check the block interval counter and determine to start a block transfer clt ( note 1 ) cld ( note 2 ) push register to stac k note 1: when using the index x mode flag (t). note 2: when using the decimal mode flag (d). push the register used in the interrupt processing routine into the stack p o p r e g i s t e r s p o p r e g i s t e r s w h i c h i s p u s h e d t o s t a c k
3886 group user s manual application 2.4 serial i/o control in the slave unit after setting the relevant registers as shown in figure 2.4.34, the slave unit becomes the state where a synchronous clock can be received at any time, and the serial i/o1 receive interrupt request bit is set to 1 each time an 8-bit synchronous clock is received. in the serial i/o1 receive interrupt processing routine, the data to be transmitted next is written to the transmit buffer register after the received data is read out. however, if no serial i/o1 receive interrupt occurs for a certain time (heading adjustment time or more), the following processing will be performed. 1. the first 1-byte data of the transmission data in the block is written into the transmit buffer register. 2. the data to be received next is processed as the first 1 byte of the received data in the block. figure 2.4.36 shows a control procedure of the slave unit using the serial i/o1 receive interrupt and any timer interrupt (for heading adjustment). fig. 2.4.36 control procedure of slave unit write a transmission data r e a d a r e c e p t i o n d a t a n w i t h i n a b l o c k t r a n s f e r t e r m ? y y a received byte counter 8? n r t i w r i t e d u m m y d a t a ( f f 1 6 ) a r e c e i v e d b y t e c o u n t e r + 1 h e a d i n g a d j u s t m e n t c o u n t e r i n i t i a l v a l u e ( n o t e 3 ) s e r i a l i / o 1 r e c e i v e i n t e r r u p t p r o c e s s i n g r o u t i n e t i m e r i n t e r r u p t p r o c e s s i n g r o u t i n e heading adjustment counter 1 n h e a d i n g a d j u s t m e n t c o u n t e r = 0 ? y r t i w r i t e t h e f i r s t t r a n s m i s s i o n d a t a ( f i r s t b y t e ) i n a b l o c k a r e c e i v e d b y t e c o u n t e r 0 c o n f i r m a t i o n o f t h e r e c e i v e d b y t e c o u n t e r t o j u d g e t h e b l o c k t r a n s f e r t e r m c l t ( n o t e 1 ) c l d ( n o t e 2 ) p u s h r e g i s t e r t o s t a c k push the register used in the interrupt processing routine into the stack clt ( note 1 ) cld ( note 2 ) push register to stac k p u s h t h e r e g i s t e r u s e d i n t h e i n t e r r u p t p r o c e s s i n g r o u t i n e i n t o t h e s t a c k p o p r e g i s t e r s p o p r e g i s t e r s w h i c h i s p u s h e d t o s t a c k p o p r e g i s t e r s pop registers which is pushed to stack notes 1: when using the index x mode flag (t). 2: when using the decimal mode flag (d). 3: in this example, set the value which is equal to the heading adjustment time divided by the timer interrupt cycle as the initial value of the heading adjustment counter. for example: when the heading adjustment time is 8 ms and the timer interrupt cycle is 1 ms, set 8 as the initial value.
3886 group user s manual application 2-67 2.4 serial i/o (4) communication (transmit/receive) using asynchronous serial i/o (uart) outline : 2-byte data is transmitted and received, using the asynchronous serial i/o. port p4 0 is used for communication control. figure 2.4.37 shows a connection diagram, and figure 2.4.38 shows a timing chart. fig. 2.4.37 connection diagram (communication using uart) specifications : the serial i/o1 is used (uart is selected). transfer bit rate : 9600 bps (f(x in ) = 4.9152 mhz is divided by 512) communication control using port p4 0 (the output level of port p4 0 is controlled by software.) 2-byte data is transferred from the transmitting side to the receiving side at intervals of 10 ms generated by the timer. fig. 2.4.38 timing chart (using uart) t r a n s m i t t i n g s i d e p 4 0 3886 group p 4 0 3 8 8 6 g r o u p r e c e i v i n g s i d e t x dr x d p 4 0 10 ms d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s t s p ( 2 ) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp( 2 ) d 0 s t . . . . . . t x d . ..... ~ ~ ~ ~
3886 group user s manual application 2.4 serial i/o brg count source brg setting value transfer bit rate (bps) (note 2) (note 1) at f(x in ) = 4.9152 mh z at f(x in ) = 8 mh z f(x in )/4 255(ff 16 ) 300 488.28125 f(x in )/4 127(7f 16 ) 600 976.5625 f(x in )/4 63(3f 16 ) 1200 1953.125 f(x in )/4 31(1f 16 ) 2400 3906.25 f(x in )/4 15(0f 16 ) 4800 7812.5 f(x in )/4 7(07 16 ) 9600 15625 f(x in )/4 3(03 16 ) 19200 31250 f(x in )/4 1(01 16 ) 38400 62500 f(x in ) 3(03 16 ) 76800 125000 f(x in ) 1(01 16 ) 153600 250000 f(x in ) 0(00 16 ) 307200 500000 notes 1: select the brg count source with bit 0 of the serial i/o1 control register (address : 1a 16 ). 2: equation of transfer bit rate: ? m: when bit 0 of the serial i/o1 control register (address : 1a 16 ) is set to 0, a value of m is 1. when bit 0 of the serial i/o1 control register (address : 1a 16 ) is set to 1, a value of m is 4. table 2.4.1 shows setting examples of the baud rate generator (brg) values and transfer bit rate values; figure 2.4.39 shows registers setting relevant to the transmitting side; figure 2.4.40 shows registers setting relevant to the receiving side. table 2.4.1 setting examples of baud rate generator values and transfer bit rate values transfer bit rate (bps) = (brg setting value + 1) ? 16 ? m ? f(x in )
3886 group user s manual application 2-69 2.4 serial i/o fig. 2.4.39 registers setting relevant to transmitting side serial i/o1 status register (address : 19 16 ) s i o 1 s t s t r a n s m i t t i n g s i d e b a u d r a t e g e n e r a t o r ( a d d r e s s : 1 c 1 6 ) b r g 7 sio1co n 1001 01 0 uart control register (address : 1b 16 ) u a r t c o n0 01 0 f(x in ) t r a n s f e r b i t r a t e ? 1 6 ? m 1 b 7 b 0 s e r i a l i / o 1 c o n t r o l r e g i s t e r ( a d d r e s s : 1 a 1 6 ) b 7 b 0 b 7 b 0 b 7 b 0 s e t w h e n b i t 0 o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r ( a d d r e s s : 1 a 1 6 ) i s s e t t o 0 , a v a l u e o f m i s 1 . w h e n b i t 0 o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r ( a d d r e s s : 1 a 1 6 ) i s s e t t o 1 , a v a l u e o f m i s 4 . ? ? b r g c o u n t s o u r c e s e l e c t i o n b i t : f ( x i n ) / 4 serial i/o1 synchronous clock selection bit : brg/16 t r a n s m i t e n a b l e b i t : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t : r e c e i v e d i s a b l e d serial i/o1 mode selection bit : asynchronous serial i/o(uart) serial i/o1 enable bit : serial i/o1 enabled s rdy1 output enable bit : s rdy1 out disabled c h a r a c t e r l e n g t h s e l e c t i o n b i t : 8 b i t s parity enable bit : parity checking disabled p 4 5 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t : c m o s o u t p u t s t o p b i t l e n g t h s e l e c t i o n b i t : 2 s t o p b i t s t r a n s m i t b u f f e r e m p t y f l a g c o n f i r m t h a t t h e d a t a h a s b e e n t r a n s f e r r e d f r o m t r a n s m i t b u f f e r r e g i s t e r t o t r a n s m i t s h i f t r e g i s t e r . w h e n t h i s f l a g i s 1 , i t i s p o s s i b l e t o w r i t e t h e n e x t t r a n s m i s s i o n d a t a i n t o t r a n s m i t b u f f e r r e g i s t e r . transmit shift register shift completion flag confirm completion of transmitting 1-byte data with this flag. 1 : transmit shift completed
3886 group user s manual application 2.4 serial i/o fig. 2.4.40 registers setting relevant to receiving side r e c e i v i n g s i d e serial i/o1 status register (address : 19 16 ) s i o 1 s t s b r g 7 serial i/o1 control register (address : 1a 16 ) sio1co n 10 0 101 0 uartcon 0 10 b 7 b 0 b 7 b 0 uart control register (address : 1b 16 ) b 7 b 0 c h a r a c t e r l e n g t h s e l e c t i o n b i t : 8 b i t s p a r i t y e n a b l e b i t : p a r i t y c h e c k i n g d i s a b l e d s t o p b i t l e n g t h s e l e c t i o n b i t : 2 s t o p b i t s b a u d r a t e g e n e r a t o r ( a d d r e s s : 1 c 1 6 ) b 7 b 0 f(x in ) t r a n s f e r b i t r a t e ? 1 6 ? m 1 set w h e n b i t 0 o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r ( a d d r e s s : 1 a 1 6 ) i s s e t t o 0 , a v a l u e o f m i s 1 . w h e n b i t 0 o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r ( a d d r e s s : 1 a 1 6 ) i s s e t t o 1 , a v a l u e o f m i s 4 . ? ? brg count source selection bit : f(x in )/4 serial i/o1 synchronous clock selection bit : brg/16 t r a n s m i t e n a b l e b i t : t r a n s m i t d i s a b l e d r e c e i v e e n a b l e b i t : r e c e i v e e n a b l e d s e r i a l i / o 1 m o d e s e l e c t i o n b i t : a s y n c h r o n o u s s e r i a l i / o ( u a r t ) serial i/o1 enable bit : serial i/o1 enabled s r d y 1 o u t p u t e n a b l e b i t : s r d y 1 o u t d i s a b l e d r e c e i v e b u f f e r f u l l f l a g confirm completion of receiving 1-byte data with this flag. 1 : a t c o m p l e t i n g r e c e p t i o n 0 : a t r e a d i n g o u t c o n t e n t s o f r e c e i v e b u f f e r r e g i s t e r o v e r r u n e r r o r f l a g 1 : w h e n d a t a i s r e a d y i n r e c e i v e s h i f t r e g i s t e r w h i l e r e c e i v e b u f f e r r e g i s t e r c o n t a i n s t h e d a t a . p a r i t y e r r o r f l a g 1 : w h e n a p a r i t y e r r o r o c c u r s i n e n a b l e d p a r i t y . framing error flag 1 : w h e n s t o p b i t s c a n n o t b e d e t e c t e d a t t h e s p e c i f i e d t i m i n g . summing error flag 1 : w h e n a n y o n e o f t h e f o l l o w i n g e r r o r s o c c u r s . overrun error parity error framing error
3886 group user s manual application 2-71 2.4 serial i/o figure 2.4.41 shows a control procedure of the transmitting side, and figure 2.4.42 shows a control procedure of the receiving side. fig. 2.4.41 control procedure of transmitting side s i o 1 s t s ( a d d r e s s : 1 9 1 6 ) , b i t 0 ? r e s e t c o m m u n i c a t i o n c o m p l e t i o n ( a d d r e s s : 1 a 1 6 ) ( a d d r e s s : 1 b 1 6 ) ( a d d r e s s : 1 c 1 6 ) ( a d d r e s s : 0 8 1 6 ) , b i t 0 ( a d d r e s s : 0 9 1 6 ) p 4 ( a d d r e s s : 0 8 1 6 ) , b i t 0 1 p a s s 1 0 m s ? y n tb/rb (address : 18 16 ) the second byte of a transmission data 1 0 s i o 1 s t s ( a d d r e s s : 1 9 1 6 ) , b i t 2 ? 1 0 initialization s i o 1 c o n u a r t c o n b r g p 4 p 4 d 1 0 0 1 x 0 0 1 2 0 0 0 0 1 0 0 0 2 8 1 . . . . . tb/rb (address : 18 16 ) t h e f i r s t b y t e o f a t r a n s m i s s i o n d a t a p4 (address : 08 16 ), bit0 0 1 0 p o r t p 4 0 s e t f o r c o m m u n i c a t i o n c o n t r o l an interval of 10 ms generated by timer communication start transmission data write transmit buffer empty flag is set to 0 by this writing. transmission data write transmit buffer empty flag is set to 0 by this writing. j u d g m e n t o f t r a n s f e r r i n g d a t a f r o m t r a n s m i t b u f f e r r e g i s t e r t o t r a n s m i t s h i f t r e g i s t e r ( t r a n s m i t b u f f e r e m p t y f l a g ) judgment of transferring data from transmit buffer register to transmit shift register (transmit buffer empty flag) j u d g m e n t o f s h i f t c o m p l e t i o n o f t r a n s m i t s h i f t r e g i s t e r ( t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ) sio1sts (address : 19 16 ), bit0? 0 xxxxxxx1 2 x: this bit is not used here. set it to 0 or 1 arbitrarily.
3886 group user s manual application 2.4 serial i/o fig. 2.4.42 control procedure of receiving side ( a d d r e s s : 1 a 1 6 ) ( a d d r e s s : 1 b 1 6 ) ( a d d r e s s : 1 c 1 6 ) ( a d d r e s s : 0 9 1 6 ) r e s e t j u d g m e n t o f c o m p l e t i o n o f r e c e i v i n g ( r e c e i v e b u f f e r f u l l f l a g ) sio1sts (address : 19 16 ), bit1? 1 0 r e a d o u t a r e c e p t i o n d a t a f r o m r b ( a d d r e s s : 1 8 1 6 ) s i o 1 s t s ( a d d r e s s : 1 9 1 6 ) , b i t 6 ? 0 1 i n i t i a l i z a t i o n s i o 1 c o n u a r t c o n b r g p 4 d 1 0 1 0 x 0 0 1 2 0 0 0 0 1 0 0 0 2 8 1 x x x x x x x 0 2 . . . . . s i o 1 s t s ( a d d r e s s : 1 9 1 6 ) , b i t 1 ? 1 0 judgment of an error flag sio1sts (address : 19 16 ), bit6? 0 1 p 4 ( a d d r e s s : 0 8 1 6 ) , b i t 0 ? 0 1 s i o 1 c o n ( a d d r e s s : 1 a 1 6 ) s i o 1 c o n ( a d d r e s s : 1 a 1 6 ) 0 0 0 0 x 0 0 1 2 1 0 1 0 x 0 0 1 2 processing for error r e a d o u t a r e c e p t i o n d a t a f r o m r b ( a d d r e s s : 1 8 1 6 ) r e c e p t i o n o f t h e f i r s t b y t e d a t a r e c e i v e b u f f e r f u l l f l a g i s s e t t o 0 b y r e a d i n g d a t a . judgment of completion of receiving (receive buffer full flag) reception of the second byte data receive buffer full flag is set to 0 by reading data. judgment of an error flag c o u n t e r m e a s u r e f o r a b i t s l i p p a g e x: this bit is not used here. set it to 0 or 1 arbitrarily.
3886 group user s manual application 2-73 2.4 serial i/o 2.4.6 notes on serial i/o (1) notes when selecting clock synchronous serial i/o (serial i/o1) ? stop of transmission operation clear the serial i/o1 enable bit and the transmit enable bit to 0 (serial i/o1 and transmit disabled). reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to 0 (serial i/o1 disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to 1 at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. ? stop of receive operation clear the receive enable bit to 0 (receive disabled), or clear the serial i/o1 enable bit to 0 (serial i/o1 disabled). ? stop of transmit/receive operation clear the transmit enable bit and receive enable bit to 0 simultaneously (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial i/o mode, any one of data transmission and reception cannot be stopped.) reason in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also operates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to 0 (transmit disabled). also, the transmission circuit is not initialized by clearing the serial i/o1 enable bit to 0 (serial i/o1 disabled) (refer to (1) ? ).
3886 group user s manual application 2.4 serial i/o (2) notes when selecting clock asynchronous serial i/o (serial i/o1) ? stop of transmission operation clear the transmit enable bit to 0 (transmit disabled). reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to 0 (serial i/o1 disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to 1 at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. ? stop of receive operation clear the receive enable bit to 0 (receive disabled). ? stop of transmit/receive operation only transmission operation is stopped. clear the transmit enable bit to 0 (transmit disabled). reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to 0 (serial i/o1 disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to 1 at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. only receive operation is stopped. clear the receive enable bit to 0 (receive disabled). (3) s rdy1 output of reception side (serial i/o1) when signals are output from the s rdy1 pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy1 output enable bit, and the transmit enable bit to 1 (transmit enabled). (4) setting serial i/o1 control register again (serial i/o1) set the serial i/o1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to 0. fig. 2.4.43 sequence of setting serial i/o1 control register again c l e a r b o t h t h e t r a n s m i t e n a b l e b i t ( t e ) a n d t h e r e c e i v e e n a b l e b i t ( r e ) t o 0 s e t t h e b i t s 0 t o 3 a n d b i t 6 o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r s e t b o t h t h e t r a n s m i t e n a b l e b i t ( t e ) a n d t h e r e c e i v e e n a b l e b i t ( r e ) , o r o n e o f t h e m t o 1 can be set with the ldm instruction at the same time
3886 group user s manual application 2-75 2.4 serial i/o (5) data transmission control with referring to transmit shift register completion flag (serial i/o1) the transmit shift register completion flag changes from 1 to 0 with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. (6) transmission control when external clock is selected (serial i/o1) when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to 1 at h of the s clk input level. also, write the transmit data to the transmit buffer register (serial i/o shift register) at h of the s clk input level. (7) transmit interrupt request when transmit enable bit is set (serial i/o1) when the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown in the following sequence. ? set the interrupt enable bit to 0 (disabled) with clb instruction. ? prepare serial i/o for transmission/reception. ? set the interrupt request bit to 0 with clb instruction after 1 or more instruction has been executed. ? set the interrupt enable bit to 1 (enabled). reason when the transmission enable bit is set to 1 , the transmit buffer empty flag and transmit shift register completion flag are set to 1 . the interrupt request is generated and the transmission interrupt bit is set regardless of which of the two timings listed below is selected as the timing for the transmission interrupt to be generated. transmit buffer empty flag is set to 1 transmit shift register completion flag is set to 1 (8) transmit data writing (serial i/o2) in the clock synchronous serial i/o, when selecting an external clock as synchronous clock, write the transmit data to the serial i/o2 register (serial i/o shift register) at h of the transfer clock input level.
3886 group user? manual application 2.5 multi-master i 2 c-bus interface 2.5 multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communication circuit, conforming to the philips i 2 c-bus data transfer format. this paragraph explains the overview and the communication example. 2.5.1 memory map fig. 2.5.1 memory map of registers relevant to i 2 c-bus interface 2.5.2 relevant registers fig. 2.5.2 structure of i 2 c data shift register ~ ~ ~ ~ 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 003e 16 003f 16 i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c a d d r e s s r e g i s t e r ( s 0 d ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r ( s 2 d ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 9 1 6 interrupt source selection register (intsel) ~ ~ ~ ~ ~ ~ ~ ~ b 7b 6b 5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? i 2 c d a t a s h i f t r e g i s t e r i 2 c data shift register (s0) [address : 12 16 ] t h i s r e g i s t e r i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a o r w r i t e t r a n s m i t d a t a . n o t e : s e c u r e 8 m a c h i n e c y c l e s f r o m c l e a r i n g m s t b i t t o 0 ( s l a v e m o d e ) u n t i l w r i t i n g d a t a t o i 2 c d a t a s h i f t r e g i s t e r . i f e x e c u t i n g t h e r e a d - m o d i f y - w r i t e i n s t r u c t i o n ( s e b , c l b e t c . ) f o r t h i s r e g i s t e r d u r i n g t r a n s f e r , d a t a m a y b e c o m e a v a l u e n o t i n t e n d e d .
3886 group user s manual application 2-77 2.5 multi-master i 2 c-bus interface fig. 2.5.3 structure of i 2 c address register fig. 2.5.4 structure of i 2 c status register b7 b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 i 2 c a d d r e s s r e g i s t e r ( s 0 d ) [ a d d r e s s : 1 3 ] r e a d / w r i t e b i t ( r w b ) 0 : write bit 1 : read bit 0 0 0 n o t e : i f t h e r e a d - m o d i f y - w r i t e i n s t r u c t i o n ( s e b , c l b , e t c . ) i s e x e c u t e d f o r t h i s r e g i s t e r a t d e t e c t i n g t h e s t o p c o n d i t i o n , d a t a m a y b e c o m e a v a l u e n o t t o i n t e n d . i 2 c a d d r e s s r e g i s t e r 1 6 s l a v e a d d r e s s ( s a d 0 , s a d 1 , s a d 2 , s a d 3 , s a d 4 , s a d 5 , s a d 6 ) t h e s e b i t s a r e c o m p a r e d w i t h t h e a d d r e s s d a t a t r a n s m i t t e d f r o m t h e m a s t e r . b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 1 0 0 i 2 c status register (s1) [address : 14 16 ] i 2 c s t a t u s r e g i s t e r 0 ? l a s t r e c e i v e b i t ( l r b ) b u s b u s y f l a g ( b b ) a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) 0 : not detected 1 : detected ( note1 ) communication mode specification bits (trx, mst) 00 : slave receive mode 01 : slave transmit mode 10 : master receive mode 11 : master transmit mode 0 0 0 : last bit = 0 1 : last bit = 1 ( note1 ) g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) 0 : no general call detected 1 : general call detected( note1, 2 ) s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) 0 : address disagreement 1 : address agreement ( note1, 2 ) ? ? ? ? scl pin low hold bit (pin) 0 : scl pin low hold 1 : scl pin low release n o t e s 1 : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n o t b e w r i t t e n . 2 : t h e s e b i t s c a n b e d e t e c t e d w h e n d a t a f o r m a t s e l e c t i o n b i t ( a l s ) o f i c c o n t r o l r e g i s t e r i s 0 . 3 : d o n o t e x e c u t e t h e r e a d - m o d i f y - w r i t e i n s t r u c t i o n ( s e b , c l b ) f o r t h i s r e g i s t e r b e c a u s e a l l b i t s o f t h i s r e g i s t e r a r e c h a n g e d b y h a r d w a r e . : 1 c a n b e w r i t t e n t o t h i s b i t , b u t 0 c a n n o t b e w r i t t e n b y p r o g r a m . 2 0 : bus free 1 : bus busy ? ?
3886 group user s manual application 2.5 multi-master i 2 c-bus interface fig. 2.5.5 structure of i 2 c control register i 2 c c o n t r o l r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 i 2 c c o n t r o l r e g i s t e r ( s 1 d ) [ a d d r e s s : 1 5 1 6 ] bit counter (number of transmit/receive bits) (bc0, bc1, bc2) 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 b 2 b 1 b 0 i 2 c - b u s i n t e r f a c e e n a b l e b i t ( e s 0 ) 0 : d i s a b l e d 1 : e n a b l e d d a t a f o r m a t s e l e c t i o n b i t ( a l s ) 0 : a d d r e s s i n g f o r m a t 1 : f r e e d a t a f o r m a t a d d r e s s i n g f o r m a t s e l e c t i o n b i t ( 1 0 b i t s a d ) 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t system clock stop selection bit (clkstp) i 2 c - b u s i n t e r f a c e p i n i n p u t l e v e l s e l e c t i o n b i t ( t i s s ) 0 : system clock stop when executing wit or stp instruction 1 : not system clock stop when executing wit instruction (do not use the stp instruction.) 0 : c m o s i n p u t 1 : s m b u s i n p u t notes : when the read-modify-write instruction is executed for this register at detecting the start condition or at completing the byte transfer, data may become a value not intended.
3886 group user s manual application 2-79 2.5 multi-master i 2 c-bus interface table 2.5.1 set value of i 2 c clock control register and scl frequency scl frequency ( note 1 ) (at = 4 mhz, unit : khz) setting value of ccr4 ccr0 standard clock mode setting disabled setting disabled setting disabled high-speed clock mode ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 setting disabled setting disabled setting disabled 34.5 33.3 32.3 100 83.3 333 250 400 (note 3) 166 (note 2) (note 2) 500/ccr value 1000/ccr value 17.2 16.6 16.1 notes 1: duty of s cl clock output is 50 %. the duty becomes 35 to 45 % only when the high-speed clock mode is selected and ccr value = 5 (400 khz, at = 4 mhz). h duration of the clock fluctuates from 4 to +2 machine cycles in the standard clock mode, and fluctuates from 2 to +2 machine cycles in the high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because l duration is extended instead of h duration reduction. these are value when s cl clock synchronization by the synchronous function is not performed. ccr value is the decimal notation value of the s cl frequency control bits ccr4 to ccr0. 2: each value of s cl frequency exceeds the limit at = 4 mhz or more. when using these setting value, use of 4 mhz or less. 3: the data formula of s cl frequency is described below: /(8 ? ccr value) standard clock mode /(4 ? ccr value) high-speed clock mode (ccr value 5) /(2 ? ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as ccr value regardless of frequency. set 100 khz (max.) in the standard clock mode and 400 khz (max.) in the high-speed clock mode to the s cl frequency by setting the s cl frequency control bits ccr4 to ccr0. fig. 2.5.6 structure of i 2 c clock control register b 7b6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 2 3 4 5 6 7 n a m e i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) [ a d d r e s s : 1 6 1 6 ] i 2 c c l o c k c o n t r o l r e g i s t e r 0 0 0 1 s c l f r e q u e n c y c o n t r o l b i t s ( c c r 0 , c c r 1 , c c r 2 , c c r 3 , c c r 4 ) 0 : s t a n d a r d c l o c k m o d e 1 : h i g h - s p e e d c l o c k m o d e s c l m o d e s p e c i f i c a t i o n b i t ( f a s t m o d e ) a c k b i t ( a c k b i t ) a c k c l o c k b i t ( a c k ) 0 : a c k i s r e t u r n e d 1 : a c k i s n o t r e t u r n e d 0 : n o a c k c l o c k 1 : a c k c l o c k r e f e r t o t a b l e 2 . 5 . 1 0
3886 group user s manual application 2.5 multi-master i 2 c-bus interface fig. 2.5.7 structure of i 2 c start/stop condition control register fig. 2.5.8 structure of interrupt source selection register b 7b 6b 5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 2 3 4 5 6 7 name 0 i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r ( s 2 d ) [ a d d r e s s : 1 7 1 6 ] i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r 0 ? 1 s t a r t / s t o p c o n d i t i o n s e t b i t ( s s c 0 , s s c 1 , s s c 2 , s s c 3 , s s c 4 )( n o t e ) 0 : falling edge active 1 : rising edge active s c l / s d a i n t e r r u p t p i n p o l a r i t y s e l e c t i o n b i t ( s i p ) s c l / s d a i n t e r r u p t p i n s e l e c t i o n b i t ( s i s ) s c l r e l e a s e t i m e = ( s ) ? ( s s c + 1 ) s e t u p t i m e = ( s ) ? ( s s c + 1 ) / 2 h o l d t i m e = ( s ) ? ( s s c + 1 ) / 2 0 : s da valid 1 : s cl valid s t a r t / s t o p c o n d i t i o n g e n e r a t i n g s e l e c t i o n b i t ( s t s p s e l ) 0 0 : setup/hold time short mode 1 : setup/hold time long mode n o t e : d o n o t s e t 0 0 0 0 0 2 o r a n o d d n u m b e r t o t h e s t a r t / s t o p c o n d i t i o n s e t b i t ( s s c 4 t o s s c 0 ) . interrupt source selection register b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t s o u r c e s e l e c t i o n b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 0 i n t e r r u p t 1 : i n p u t b u f f e r f u l l i n t e r r u p t int 2 /i 2 c interrupt source selection bit cntr 1 /key-on wake-up interrupt source selection bit 0 : int 1 interrupt 1 : output buffer empty interrupt serial i/o1 transmit/s cl ,s da interrupt source selection bit c n t r 0 / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : serial i/o1 transmit interrupt 1 : s cl ,s da interrupt 0 : c n t r 0 i n t e r r u p t 1 : s c l , s d a i n t e r r u p t s e r i a l i / o 2 / i 2 c i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : serial i/o2 interrupt 1 : i 2 c interrupt 0 : int 2 interrupt 1 : i 2 c interrupt 0 : c n t r 1 i n t e r r u p t 1 : k e y - o n w a k e - u p i n t e r r u p t a d c o n v e r t e r / k e y - o n w a k e - u p i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : a - d c o n v e r t e r i n t e r r u p t 1 : k e y - o n w a k e - u p i n t e r r u p t ? 1 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 2 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 3 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . interrupt source selection register [intsel: address 0039 16 ] ? 1 ? 2 ? 2 ? 3 ? 3 ? 1
3886 group user s manual application 2-81 2.5 multi-master i 2 c-bus interface fig. 2.5.9 structure of interrupt request register 1 fig. 2.5.10 structure of interrupt request register 2 interrupt request register 1 b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s : 3 c 1 6 ] i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t r e q u e s t b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued timer y interrupt request bit timer 1 interrupt request bit ? : t h e s e b i t s c a n b e c l e a r e d t o 0 b y p r o g r a m , b u t c a n n o t b e s e t t o 1 . 0 : no interrupt request issued 1 : interrupt request issued s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued t i m e r x i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? t i m e r 2 i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued ? interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . ? c n t r 0 / s c l , s d a i n t e r r u p t r e q u e s t b i t cntr 1 /key-on wake-up interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued int 4 interrupt request bit ad converter/key-on wake-up interrupt request bit ? : t h e s e b i t s c a n b e c l e a r e d t o 0 b y p r o g r a m , b u t c a n n o t b e s e t t o 1 . 0 : no interrupt request issued 1 : interrupt request issued serial i/o2/i 2 c interrupt request bit i n t 2 / i 2 c i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued int 3 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ?
3886 group user s manual application 2.5 multi-master i 2 c-bus interface fig. 2.5.11 structure of interrupt control register 1 fig. 2.5.12 structure of interrupt control register 2 interrupt control register 1 b 7b 6b5b 4b 3b 2b 1b 0 b f u n c t i o n a t reset rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s : 3 e 1 6 ] i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t e n a b l e b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled timer y interrupt enable bit timer 1 interrupt enable bit s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled t i m e r 2 i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] f i x t h i s b i t t o 0 . c n t r 0 / s c l , s d a i n t e r r u p t e n a b l e b i t cntr 1 /key-on wake-up interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled int 4 interrupt enable bit ad converter/key-on wake-up interrupt enable bit serial i/o2/i 2 c interrupt enable bit i n t 2 / i 2 c i n t e r r u p t e n a b l e b i t i n t 3 i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0
3886 group user s manual application 2-83 2.5 multi-master i 2 c-bus interface 2.5.3 i 2 c-bus overview the i 2 c-bus is a both directions serial bus connected with two signal lines; the scl which transmits a clock and the sda which transmits data. each port has an n-channel open-drain structure for output and a cmos structure for input. the devices connected with the i 2 c-bus interface use an open drain, so that external pull-up resistors are required. accordingly, while any one of devices always outputs l , other devices cannot output h . figure 2.5.13 shows the i 2 c-bus connection structure. fig. 2.5.13 i 2 c-bus connection structure s c l o u t p u t s c l i n p u t s d a o u t p u t sda input scl output scl inpu t sda output sda input scl output scl inpu t sda output sda input
3886 group user s manual application 2.5 multi-master i 2 c-bus interface 2.5.4 communication format figure 2.5.14 shows an i 2 c-bus communication format example. the i 2 c-bus consists of the following: start condition to indicate communication start slave address and data to specify each device ack to indicate acknowledgment of address and data stop condition to indicate communication completion. fig. 2.5.14 i 2 c-bus communication format example (1) start condition when communication starts, the master device outputs the start condition to the slave device. the i 2 c-bus defines that data can be changed when a clock line is l . accordingly, data change when a clock line is h is treated as stop or start condition. the data line change from h to l when a clock line is h is start condition. (2) stop condition just as in start condition, the data line change from l to h when a clock line is h is stop condition. the term from start condition to stop condition is called bus busy . the master device is inhibited from starting data transfer during that term. the bus busy status can be judged by using the bb flag of i 2 c status register (bit 5 of address 0014 16 ). (3) slave address the slave address is transmitted after start condition. this address consists of 7 bits and the 7- th bit functions as the read/write (r/w) bit which indicates a data transmission method. the slave devices connected with the same i 2 c-bus must have their addresses, individually. it is because that address is defined for the master to specify the transmitted/received slave device. the read/write (r/w) bit indicates a data transmission direction; l means write from the master to the slave, and h means read in. (4) data the data has an 8-bit length. there are two cases depending on the read/write (r/w) bit of a slave address; one is from the master to the slave and the other is from the slave to the master. s r/w a a a s c l sda p s t a r ta c k w ack ack stop b u s b u s y t e r m slave address 7 bits d a t a 8 b i t s d a t a 8 b i t s a d d r e s s e s 0 t o 6d a t a 0 t o 7 d a t a 0 t o 7
3886 group user s manual application 2-85 2.5 multi-master i 2 c-bus interface (5) ack bit the ack bit clock is generated by the master. this is used for indication of acknowledgment on the sda line, the slave s busy and the data end. for example, the slave device makes the sda line l for acknowledgment when confirming the slave address following the start condition. the built-in i 2 c-bus interface has the slave address automatic judgment function and the ack acknowledgment function. l is automatically output when the ack bit of i 2 c clock control register (bit 6 of address 0016 16 ) is 0 and an address data is received. when the slave address and the address data do not correspond, h (nack) is automatically output. in case the slave device cannot receive owing to an interrupt process, performing operation or others, the master can output stop condition and complete data transfer by making the ack data of the slave address h for acknowledgment. even in case the slave device cannot receive data during data transferring, the communication can be interrupted by performing nack acknowledgment to the following data. when the master is receiving the data from the slave, the master can notify the slave of completion of data reception by performing nack acknowledgment to the last data received from the slave. (6) restart condition the master can receive or transmit data without transmission of stop condition while the master is transmitting or receiving a data. for example, after the master transmitted a data to the slave, transmitting a slave address + r (read) following restart condition can make the following data treat as a reception data. additionally, transmitting a slave address + w (write) following restart condition can make the following data treat as a transmission data. fig. 2.5.15 restart condition of master reception 2.5.5 synchronization and arbitration lost (1) synchronization when a plural master exists on the i 2 c-bus and the masters, which have different speed, are going to simultaneously communicate; there is a rule to unify clocks so that a clock of each bit can be output correctly. figure 2.5.16 shows a synchronized scl line example. the scl (a) and the scl (b) are the master devices having a different speed. the scl is synchronized waveforms. as shown by figure 2.5.16, the scl lines can be synchronized by the following method; the device which first finishes h term makes the scl line l and the device which last remains l makes the scl line h . a sr a p r / w a r/w a a s s l a v e a d d r e s s 7 b i t s 0 8 b i t s7 bits 8 b i t s8 b i t s 1 s l a v e a d d r e s s d a t a start condition r e s t a r t c o n d i t i o n m a s t e r r e c e p t i o n 1 s t - b y t e master reception 2nd-byte nack expression end of master reception data l o w e r d a t a u p p e r d a t a master to slave slave to master s: start condition a: ack bit sr: restart condition p : s t o p c o n d i t i o n r / w : r e a d / w r i t e b i t w r i t er e a d
3886 group user s manual application 2.5 multi-master i 2 c-bus interface ? after start condition, the masters, which have different speed, simultaneously start clock transmission. ? the scl outputs l because (a) finished counting h output; then (b) s h output counting is interrupted and (b) starts counting l output. ? the (a) outputs h because (a) finished counting l term; the scl level does not become h because (b) outputs l , and counting h term does not start but stop. ? (b) outputs l term. ? the scl outputs h because (b) finished counting l term; then (b) s h output counting is started at the same time as (a). ? the scl outputs l because (a) first finished counting h output; then (b) s h output counting is interrupted and (b) starts counting l output. ? the above are repeatedly performed. (2) clock synchronization during communication in the i 2 c-bus, the slave device is permitted to retain the scl line l and become waiting status for transmission from the master. by byte unit, for the reception preparation of the slave device, the master can become waiting status by making the scl line l , which is after completion of byte reception or the ack. by bit unit, it is possible to slow down a clock speed by retaining the scl line l for slave devices having limited hardware. the 3886 group can transmit data correctly without reduction of data bits toward waiting status request from the slave device. it is because the synchronization circuit is included for the case when retaining the scl line l as an internal hardware. after the last bit, including the ack bit, of a transmission/reception data byte, the scl line automatically remains l and waiting status is generated until completion of an interrupt process or reception preparation. (3) arbitration lost a plural master exists on the same bus in the i 2 c-bus and there are possibility to start communication simultaneously. even when the master devices having the same transmission frequency start communication simultaneously, which device must transmit data correctly. accordingly, there is the definition to detect a communication confliction on the sda line in the i 2 c-bus. the sda line is output at the timing synchronized by the scl, however, the synchronization among the sda signals is not performed. fig. 2.5.16 scl waveforms when synchronizing clocks s c l ( a ) s c l ( b ) s c l ? ? ? ? ? ? ?
3886 group user s manual application 2-87 2.5 multi-master i 2 c-bus interface 2.5.6 i 2 c-bus communication usage example this clause explains a control example using the i 2 c-bus. this is a control example as the master device and the slave device in the read word protocol of i 2 c-bus protocol. the following is a communication example of e 2 prom (24c0x). communication specifications: communication frequency = 100 khz slave address of communication destination, e 2 prom, = 1010000x 2 (x means the read/write bit) address = e 2 prom internal address the communication process is performed in the interrupt process. however, the main process performs an occurrence of the first start condition and a slave address set. a communication buffer is established. data transfer between the main process and the interrupt process is performed through the communication buffer. (1) initial setting figure 2.5.17 shows an initial setting example using i 2 c-bus communication.
3886 group user s manual application 2.5 multi-master i 2 c-bus interface fig. 2.5.17 initial setting example s0 d 0 0 100 0 1 b 0 b 7 0 s 2 1 0 001 0 1 b 0 b 7 0 s 1 01 0 b 0 b 7 s 2 d 01 b 0 b 7 000 1 1 s1 d 1 00 b 0 b 7 000 1 0 1 i 2 c a d d r e s s r e g i s t e r ( a d d r e s s 1 3 1 6 ) i 2 c c l o c k c o n t r o l r e g i s t e r ( a d d r e s s 1 6 1 6 ) i 2 c status register (address 14 16 ) i 2 c start/stop condition control register (address 17 16 ) i 2 c control register (address 15 16 ) s e t s l a v e a d d r e s s v a l u e a 0 1 6 . s e t c l o c k 1 0 0 k h z ( x i n = 8 m h z ) s t a n d a r d c l o c k m o d e a c k i s r e t u r n e d a c k c l o c k scl pin low hold bit: fix to 1 slave receive mode set setup time hold time to 27 cycles (6.75 s: x in = 8 mhz). scl/sda interrupt: falling edge active scl/sda interrupt: sda valid set setup/hold time to 1 (long mode). s e t n u m b e r o f t r a n s m i t / r e c e i v e b i t s t o 8 . i 2 c - b u s i n t e r f a c e : e n a b l e d a d d r e s s i n g f o r m a t 7 - b i t a d d r e s s i n g f o r m a t s y s t e m c l o c k n o t s t o p p e d w h e n w i t i n s t r u c t i o n i s e x e c u t e d s e t c m o s i n p u t l e v e l .
3886 group user s manual application 2-89 2.5 multi-master i 2 c-bus interface (2) communication example in master device the master device follows the procedures ? to ? shown by figure 2.5.18. additionally, the shaded area in the figure is a transmission data from the master device and the white area is a transmission data from the slave device. ? generating of start condition; transmission of slave address + write bit ? transmission of command ? generating of restart condition; transmission of slave address + read bit ? reception of lower data ? reception of upper data ? generating of stop condition figures 2.5.19 to 2.5.24 show the procedures ? to ? . fig. 2.5.18 read word protocol communication as i 2 c-bus master device a sr a p r / w a r/w a a s ? ?? ? ? ? s l a v e a d d r e s s 7 b i t s 0 8 b i t s7 b i t s8 b i t s8 b i t s 1 s l a v e a d d r e s s c o m m a n d i n t e r r u p t r e q u e s t interrupt request interrupt request interrupt request i n t e r r u p t r e q u e s t l o w e r d a t a upper data m a s t e r t o s l a v e s l a v e t o m a s t e r s: start condition a: ack bit sr: restart condition p: stop condition r/w: read/write bit w r i t e read
3886 group user s manual application 2.5 multi-master i 2 c-bus interface ? generating of start condition; transmission of slave address + write bit after confirming that other master devices do not use the bus, generate the start condition, because the i 2 c-bus is a multi-master. write slave address + write bit to the i 2 c data shift register (address 0012 16 ) before performing to make the start condition generate. it is because the scl of 1-byte unit is output, following occurrence of the start condition. if other master devices start communication until an occurrence of the start condition after confirming the bus use, it cannot communicate correctly. however in this case, that situation does not affect other master devices owing to detection of an arbitration lost or the start condition duplication preventing function. fig. 2.5.19 generating of start condition and transmission process of slave address + write bit b b ( a d d r e s s 1 4 1 6 ) , b i t 5 ? ( n o t e 2 ) 0 (not used) 1 ( u s e d ) e n d ( a ) 0 0 0 1 0 1 1 0 2 s e i ( n o t e 1 ) s0(address 12 16 ) (a) s 1 ( a d d r e s s 1 4 1 6 ) 1 1 1 1 0 0 0 0 2 c l i ( n o t e 1 ) 1 i n t e r r u p t s d i s a b l e d b u s u s e c o n f i r m a t i o n start condition occurrence s l a v e a d d r e s s v a l u e w r i t e i n t e r r u p t e n a b l e d n o t e s 1 : i n t h i s e x a m p l e , t h e s e i i n s t r u c t i o n t o d i s a b l e i n t e r r u p t s n e e d n o t b e e x e c u t e d b e c a u s e t h i s p r o c e s s i n g i s g o i n g t o b e p e r f o r m e d i n t h e i n t e r r u p t p r o c e s s i n g . w h e n t h e s t a r t c o n d i t i o n i s g e n e r a t e d o u t o f t h e i n t e r r u p t p r o c e s s i n g , e x e c u t e t h e s e i i n s t r u c t i o n t o d i s a b l e i n t e r r u p t s . 2 : u s e t h e b r a n c h b i t i n s t r u c t i o n t o c o n f i r m b u s b u s y .
3886 group user s manual application 2-91 2.5 multi-master i 2 c-bus interface ? transmission of command confirm correct completion of communication at ? before command transmission. when receiving the stop condition, a process not to transmit a command is required, because the internal i 2 c- bus generates an interrupt request also owing to the stop condition transmitted to other devices. after confirming correct completion of communication, write a command to the i 2 c data shift register (address 0012 16 ). in case the al bit (bit 3 of address 0014 16 ) is 1 , check the slave address comparison flag (ass bit; bit 2 of address 0014 16 ) to judge whether the device given a right of master transmission owing to an arbitration specifies itself as a slave address. when it is 1 , perform the slave reception; when 0 , wait for a stop condition occurrence caused by other devices and the communication completion. in case the al bit is 0 , check the last received bit (lrb bit; bit 0 of address 0014 16 ). when it is 1 , make the stop condition generate and release the bus use, because the specified slave device does not exist on the i 2 c-bus. fig. 2.5.20 transmission process of command a l ( a d d r e s s 1 4 1 6 ) , b i t 3 ? a a s ( a d d r e s s 1 4 1 6 ) , b i t 2 ? 0 (ack) 0 (not detected) s t o p c o n d i t i o n o u t p u t s0 (address 12 16 ) 00001111 2 p i n ( a d d r e s s 1 4 1 6 ) , b i t 4 ? 1 ( e r r o r ) 0 (slave address transmitted) l r b ( a d d r e s s 1 4 1 6 ) , b i t 0 ? 0 ( a d d r e s s n o t c o r r e s p o n d e d ) 1 ( n a c k ) 1 (detected) 1(address corresponded) e n d 2 r e - t r a n s m i s s i o n p r e p a r a t i o n s l a v e r e c e p t i o n j u d g m e n t o f s l a v e a d d r e s s c o m p a r i s o n judgment of bus hold judgment of arbitration lost detection ack confirmation command data write to i 2 c data shift register
3886 group user s manual application 2.5 multi-master i 2 c-bus interface ? generating of restart condition; transmission of slave address + read bit confirm correct completion of communication at ? before generating the restart condition. after confirming correct completion, generate the restart condition and perform the transmission process of slave address + read bit . note that procedure because that is different from ? s process. as the same reason as ? , write slave address + read bit to the i 2 c data shift register (address 0012 16 ) before performing to make the start condition generate. however, when writing a slave address to the i 2 c data shift register in this condition, a slave address is output at that time. consequently, the restart condition cannot be generated. therefore, follow the slave reception procedure before those processes. in case the arbitration lost detecting flag (al bit, bit 3 of address 0014 16 ) is 1 , return to the process ? , because other master devices will have priority to communicate. when the last received bit (lrb bit; bit 0 of address 0014 16 ) is 1 , generate the stop condition and make the bus release, because acknowledgment cannot be done owing to busy status of the slave device specified on the i 2 c-bus or other reasons. fig. 2.5.21 transmission process of restart condition and slave address + read bit al (address 14 16 ), bit 3 ? 0 ( n o t d e t e c t e d ) 0 ( a c k ) s1(address 14 16 ) 00000000 2 ( note 1 ) l r b ( a d d r e s s 1 4 1 6 ) , b i t 0 ? 1(nack) ( a ) 0 0 0 1 0 1 1 1 2 s0(address 0012 16 ) (a) s 1 ( a d d r e s s 0 0 1 4 1 6 ) 1 1 1 1 0 0 0 0 2 s e i ( n o t e 2 ) end s t o p c o n d i t i o n o u t p u t r e - t r a n s m i s s i o n p r e p a r a t i o n 0 ( c o m m a n d t r a n s m i s s i o n ) p i n ( a d d r e s s 1 4 1 6 ) , b i t 4 ? 3 cli( note 2 ) slave address value write bus judgment during hold judgment of arbitration lost detection ack confirmation slave receive mode se t slave address read out interrupt disabled interrupt enabled restart condition occurrence 1 (stop condition) 1 ( d e t e c t e d ) n o t e s 1 : s e t t o t h e r e c e i v e m o d e w h i l e t h e p i n b i t i s 0 . d o n o t w r i t e 1 t o t h e p i n b i t . 2 : i n t h i s e x a m p l e , t h e s e i i n s t r u c t i o n t o d i s a b l e i n t e r r u p t s n e e d n o t b e e x e c u t e d b e c a u s e t h i s p r o c e s s i n g i s g o i n g t o b e p e r f o r m e d i n t h e i n t e r r u p t p r o c e s s i n g . w h e n t h e s t a r t c o n d i t i o n i s g e n e r a t e d o u t o f t h e i n t e r r u p t p r o c e s s i n g , e x e c u t e t h e s e i i n s t r u c t i o n t o d i s a b l e i n t e r r u p t s .
3886 group user s manual application 2-93 2.5 multi-master i 2 c-bus interface ? reception of lower data confirm correct completion of communication at ? before receiving the lower data. after confirming correct completion, clear the ack bit (bit 6 of address 0016 16 ) to 0 , in which ack is returned, and set to the master receive mode. after that, write dummy data to the i 2 c data shift register (address 0012 16 ). when the mst bit (bit 7 of address 0014 16 ) is 0 , perform the error process explained as follows and return to the process ? . when the last received bit (lrb bit; bit 0 of address 0014 16 ) is 1 , generate the stop condition and make the bus release, because the slave device specified on the i 2 c-bus does not exist. fig. 2.5.22 reception process of lower data 1 ( s t o p c o n d i t i o n ) a l ( a d d r e s s 1 4 1 6 ) , b i t 3 ? m s t ( a d d r e s s 1 4 1 6 ) , b i t 7 ? 0(ack) 1 ( m a s t e r ) s 2 ( a d d r e s s 1 6 1 6 ) 1 0 0 0 0 1 0 1 2 lrb (address 14 16 ), bit0 ? 0 ( s l a v e ) 1 ( n a c k ) 1 ( d e t e c t e d ) 0 ( n o t d e t e c t e d ) end re-transmission preparation error processing s1(address 14 16 ) 10100000 2 s0(address 12 16 ) 11111111 2 p i n ( a d d r e s s 1 4 1 6 ) , b i t 4 ? 0 ( t r a n s m i s s i o n o f r e s t a r t c o n d i t i o n ) master receive mode se t 4 stop condition outpu t j u d g m e n t o f b u s h o l d j u d g m e n t o f a r b i t r a t i o n l o s t d e t e c t i o n a c k c o n f i r m a t i o n a c k c l o c k i s u s e d s e l e c t a n d a c k i s r e t u r n e d s e t judgment of slave mode detection d u m m y d a t a t o i 2 c d a t a s h i f t r e g i s t e r w r i t e
3886 group user s manual application 2.5 multi-master i 2 c-bus interface ? transmission of upper data confirm correct completion of communication at ? before receiving the upper data. after confirming correct completion, store the received data (lower data). set the ack bit (bit 6 of address 0016 16 ) to 1 , in which ack is not returned and write dummy data to the i 2 c data shift register (address 0012 16 ). when the mst bit (bit 7 of address 0014 16 ) is 0 , return to the process ? , because other devices have priority to communicate. fig. 2.5.23 reception process of upper data a l ( a d d r e s s 1 4 1 6 ) , b i t 3 ? mst (address 14 16 ), bit 7 ? 1(master) r e c e i v e d a t a b u f f e r s 0 ( a d d r e s s 1 2 1 6 ) 0 ( s l a v e ) 1 ( d e t e c t e d ) 0(not detected) end re-transmission preparation error processing s2(address 16 16 ) 11000101 2 s0(address 12 16 ) 11111111 2 p i n ( a d d r e s s 1 4 1 6 ) , b i t 4 ? 1 ( s t o p c o n d i t i o n ) 0(lower data transmitted) 5 j u d g m e n t o f b u s h o l d j u d g m e n t o f a r b i t r a t i o n l o s t d e t e c t i o n n a c k i s r e t u r n e d s e t j u d g m e n t o f s l a v e m o d e d e t e c t i o n d u m m y d a t a t o i 2 c d a t a s h i f t r e g i s t e r w r i t e r e c e i v e d a t a r e a d a n d s a v e
3886 group user s manual application 2-95 2.5 multi-master i 2 c-bus interface ? generating of stop condition confirm correct completion of communication at ? before generating the stop condition. after confirming correct completion, store the received data (upper data). clear the ack bit (bit 6 of address 0016 16 ) to 0 , in which ack is returned, and generate the stop condition. the communication mode is set to the slave receive mode by the occurrence of stop condition. when the mst bit (bit 7 of address 0014 16 ) is 0 , return to the process ? , because other devices have priority to communicate. fig. 2.5.24 generating of stop condition al (address 14 16 ), bit 3 ? 1 ( d e t e c t e d ) 0 (not detected) s1(address 14 16 ) 11010000 2 e n d re-transmission preparation receive data buffer s0(address 12 16 ) s2(address 16 16 ) 10000101 2 b b ( a d d r e s s 1 4 1 6 ) , b i t 5 ? ( n o t e ) 0 ( b u s f r e e ) 1 ( b u s b u s y ) pin (address 14 16 ), bit 4 ? 1 ( s t o p c o n d i t i o n ) 0 (upper data transmitted) n o t e : u s e t h e b r a n c h b i t i n s t r u c t i o n t o c h e c k b u s b u s y . a l s o , e x e c u t e t h e t i m e o u t p r o c e s s i n g s e p a r a t e l y , i f n e c c e s s a r y . 6 j u d g m e n t o f b u s h o l d judgment of arbitration lost detection set ack is returned judgment of bus busy stop condition occurrence r e c e i v e d a t a r e a d a n d s a v e
3886 group user? manual application 2.5 multi-master i 2 c-bus interface (3) communication example in slave device the slave device follows the procedures ? to ? shown by figure 2.5.25. the only difference from the master device? communication is an occurrence of interrupt request after detection of stop condition. ? reception of start condition; transmission of ack bit due to slave address correspondence ? reception of command ? reception of restart condition; reception of slave address + read bit ? transmission of lower data ? transmission of upper data ? reception of stop condition figures 2.5.26 to 2.5.31 show the procedures ? to ? . fig. 2.5.25 communication example as slave device a sr a p r / w a r / w a a s master to slave slave to master s: start condition a: ack bit sr: restart condition p : s t o p c o n d i t i o n r / w : r e a d / w r i t e b i t ? ??? ? ? slave address 7 b i t s 0 8 b i t s7 bits 8 b i t s8 b i t s 1 s l a v e a d d r e s s command interrupt request interrupt request interrupt reques t interrupt reques t interrupt request l o w e r d a t a upper data interrupt r e write read
3886 group user s manual application 2-97 2.5 multi-master i 2 c-bus interface ? reception of start condition; transmission of ack bit due to slave address correspondence in the case of operation as the slave, all processes are performed in the interrupt after setting of the slave reception in the main process, because an interrupt request does not occur until correspondence of a slave address. in the first interrupt, after confirming correspondence of the slave address, write dummy data to receive a command into the i 2 c data shift register. fig. 2.5.26 reception process of start condition and slave address a a s ( a d d r e s s 1 4 1 6 ) , b i t 2 ? 1 ( c o r r e s p o n d e d ) 0 ( n o t c o r r e s p o n d e d ) end s0(address 12 16 ) 11111111 2 error processing pin (address 14 16 ), bit 4 ? 1 ( s t o p c o n d i t i o n ) 0(slave address received) 1 s1(address 14 16 ) 00010000 2 judgment of bus hold judgment of slave address correspondence slave receive mode set dummy data write to i 2 c data shift register
3886 group user s manual application 2.5 multi-master i 2 c-bus interface ? reception of command confirm correct completion of the command reception in the interrupt after receiving the command. after confirming correct command from the host, write dummy data to the i 2 c data shift register to wait for reception of the next slave address. fig. 2.5.27 reception process of command end s 0 ( a d d r e s s 1 2 1 6 ) 1 1 1 1 1 1 1 1 2 error end r e c e i v e d a t a b u f f e r s 0 ( a d d r e s s 1 2 1 6 ) s 2 ( a d d r e s s 1 6 1 6 ) 1 0 0 0 0 1 0 1 2 j u d g m e n t o f r e c e i v e c o m m a n d p i n ( a d d r e s s 1 4 1 6 ) , b i t 4 ? 1 ( s t o p c o n d i t i o n ) 0(command received) 2 s 1 ( a d d r e s s 1 4 1 6 ) 0 0 0 1 0 0 0 0 2 j u d g m e n t o f b u s h o l d a c k c l o c k i s u s e d s e l e c t a n d a c k i s r e t u r n e d s e t slave receive mode se t dummy data write to i 2 c data shift register r e c e i v e d a t a r e a d a n d s a v e
3886 group user s manual application 2-99 2.5 multi-master i 2 c-bus interface ? reception of restart condition and slave address after receiving a slave address, prepare transmission data. judgment whether receiving data or transmitting is required, because the mode is automatically switched between the receive mode and the transmit mode depending on the r/w bit of the received slave address. accordingly, judge whether read or write referring the slave address comparison flag (aas bit; bit 2 of address 0014 16 ). fig. 2.5.28 reception process of restart condition and slave address 1 (transmitted) end s 0 ( a d d r e s s 1 2 1 6 ) l o w e r d a t a e r r o r e n d p i n ( a d d r e s s 1 4 1 6 ) , b i t 4 ? 1 ( s t o p c o n d i t i o n ) 0 (lower data received) 3 s 1 ( a d d r e s s 1 4 1 6 ) 0 0 0 1 0 0 0 0 2 t r x ( a d d r e s s 1 4 1 6 ) , b i t 6 ? 0 ( r e c e i v e d ) end s l a v e r e c e i v e p r o c e s s i n g , e t c . judgment of bus hold judgment of transmit/receive mode s l a v e r e c e i v e m o d e s e t output lower data write to i 2 c data shift registe r
3886 group user s manual application 2.5 multi-master i 2 c-bus interface ? transmission of lower data before transmitting the upper data, restart to transmit the data at ? and confirm correct completion of transmission of the lower data set in the slave address reception interrupt. after that, transmit the upper data. fig. 2.5.29 transmission process of lower data end s 0 ( a d d r e s s 1 2 1 6 ) u p p e r d a t a error end 0(ack) l r b ( a d d r e s s 1 4 1 6 ) , b i t 0 ? 1 ( n a c k ) p i n ( a d d r e s s 1 4 1 6 ) , b i t 4 ? 1 ( s t o p c o n d i t i o n ) 0(lower data transmission completed) 4 s 1 ( a d d r e s s 1 4 1 6 ) 0 0 0 1 0 0 0 0 2 j u d g m e n t o f b u s h o l d a c k c o n f i r m a t i o n slave receive mode set o u t p u t u p p e r d a t a w r i t e t o i 2 c d a t a s h i f t r e g i s t e r
3886 group user s manual application 2-101 2.5 multi-master i 2 c-bus interface ? transmission of upper data confirm correct completion of the upper data transmission. the master returns the nack toward the transmitted second-byte data, the upper data. accordingly, confirm that the last received bit (lrb bit; bit 0 of address 0014 16 ) is 1 . after that, write dummy data to the i 2 c data shift register and wait for the interrupt of stop condition. fig. 2.5.30 transmission process of upper data end s 0 ( a d d r e s s 1 2 1 6 ) 1 1 1 1 1 1 1 1 2 error end 0 ( a c k ) l r b ( a d d r e s s 1 4 1 6 ) , b i t 0 ? 1(nack) 5 pin (address 14 16 ), bit 4 ? 1 ( s t o p c o n d i t i o n ) 0(upper data transmission completed) s1(address 14 16 ) 00010000 2 n o t e : u s e t h e b r a n c h b i t i n s t r u c t i o n t o c h e c k b u s b u s y . judgment of bus hold ack confirmation slave receive mode se t d u m m y d a t a w r i t e t o i 2 c d a t a s h i f t r e g i s t e r
3886 group user s manual application 2.5 multi-master i 2 c-bus interface ? reception of stop condition confirm that the stop condition is correctly output and the bus is released. fig. 2.5.31 reception of stop condition e n d e n d p r o c e s s i n g s1(address 14 16 ) 00010000 2 p i n ( a d d r e s s 1 4 1 6 ) , b i t 4 ? 1 ( s t o p c o n d i t i o n ) 0 ( a d d r e s s o r d a t a r e c e i v e d ) error end 6 s1(address 14 16 ) 00010000 2 j u d g m e n t o f b u s h o l d slave receive mode set s l a v e r e c e i v e m o d e s e t
3886 group user? manual 2-103 application 2.5 multi-master i 2 c-bus interface 2.5.7 notes on multi-master i 2 c-bus interface (1) read-modify-write instruction precautions for read-modify-write instructions, such as seb and clb , when used for any of the registers of the multi-master i 2 c-bus interface, are described below. ? i 2 c data shift register (s0: address 0012 16 ) when executing the read-modify-write instruction for this register during transfer, data may become an unexpected value. ? i 2 c address register (s0d: address 0013 16 ) when the read-modify-write instruction is executed for this register at detecting the stop condition, data may become an unexpected value. reason because hardware changes the read/write bit (rwb) at detecting the stop condition. ? i 2 c status register (s1: address 0014 16 ) do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. ? i 2 c control register (s1d: address 0015 16 ) when the read-modify-write instruction is executed for this register at detecting the start condition or at completing the byte transfer, data may become an unexpected value. reason because hardware changes the bit counter (bc0 to bc2). ? i 2 c clock control register (s2: address 0016 16 ) the read-modify-write instruction can be executed for this register. ? i 2 c start/stop condition control register (s2d: address 0017 16 ) the read-modify-write instruction can be executed for this register.
3886 group user? manual 2.5 multi-master i 2 c-bus interface application (2) procedure for generating start condition using multi-master ? procedure example (the necessary conditions for the procedure are described in items ? to ? below). lda #sladr (take out slave address value) sei (disable interrupt) bbs 5, s1, busbusy (bb flag confirmation and branch process) busfree: sta s0 (write slave address value) ldm #$f0, s1 (trigger start condition generation) cli (enable interrupt) : : busbusy: cli (enable interrupt) : : ? use ?ranch on bit set?of ?bs 5, s1, for the bb flag confirmation and branch process. ? use ?ta? ?tx?or ?ty?of the zero page addressing instruction for writing the slave address value to the i 2 c data shift register (s0: address 0012 16 ). ? execute the branch instruction of above ? and the store instruction of above ? continuously shown the above procedure example. ? disable interrupts during the following three process steps: ?bb flag confirmation ?write slave address value ?trigger start condition generation when the bb flag is in bus busy state, enable interrupts immediately. (3) procedure for generating restart condition this procedure cannot be applied to m3886 7m8a and m3886 7e8a when the external memory is used and the bus cycle is extended by onw function. ? procedure example (the necessary conditions for the procedure are described in items ? to ? below). execute the following procedure when the pin bit is ?? ldm #$00, s1 (select slave receive mode) lda #sladr (take out slave address value) sei (disable interrupt) sta s0 (write slave address value) ldm #$f0, s1 (trigger restart condition generation) cli (enable interrupt) : : ? select the slave receive mode when the pin bit is ?? do not write ??to the pin bit. neither ??nor ??is specified as input to the bb bit. the trx bit becomes ??and the sda pin is released. ? the scl pin is released by writing the slave address value to the i 2 c data shift register. ? disable interrupts during the following two process steps: ?write slave address value ?trigger restart condition generation (4) writing to i 2 c status register do not execute an instruction to set the pin bit to ??from ??and an instruction to set the mst and trx bits to ??from ??simultaneously. because it may enter the state that the scl pin is released and the sda pin is released after about one machine cycle. do not execute an instruction to set the mst and trx bits to ??from ??simultaneously when the pin bit is ?? because it may become the same as above.
3886 group user? manual 2-105 application 2.5 multi-master i 2 c-bus interface (5) process of after stop condition generating do not write data in the i 2 c data shift register (s0) and the i 2 c status register (s1) until the bus busy flag bb becomes ??after generating the stop condition in the master mode. because the stop condition waveform might not be normally generated. reading to the above registers does not have the problem. (6) stop condition input at 7th clock pulse the sda line may be held at low even if flag bb is set to ??when all the following conditions are satisfied: ?he stop condition is input at the 7th clock pulse while receiving a slave address or data. ?he clock pulse is continuously input. ?n the slave mode countermeasure: write dummy data to the i 2 c data shift register or reset the es0 bit in the s1d register (es0 = ? es0 = ?? during a stop condition interrupt routine with flag bb = ?? note: do not use the read-modify-write instruction at this time. furthermore, when the es0 bit is set to ?? the sda pin becomes a general-purpose port ; so that the port must be set to input mode or output ?? (7) es0 bit switch in standard clock mode when ssc = ?0010 2 ?or in high-speed clock mode, flag bb may switch to ??if es0 bit is set to ??when sda is ?? countermeasure: set es0 to 1 when sda is h .
3886 group user? manual application 2-106 2.6 pwm 2.6 pwm this paragraph explains the registers setting method and the notes relevant to the pwm. 2.6.1 memory map fig. 2.6.1 memory map of registers relevant to pwm 0034 16 a d / d a c o n t r o l r e g i s t e r ( a d c o n ) 0 0 3 0 1 6 0 0 3 1 1 6 p w m 0 h r e g i s t e r ( p w m 0 h ) p w m 0 l r e g i s t e r ( p w m 0 l ) 0 0 2 e 1 6 p o r t c o n t r o l r e g i s t e r 1 ( p c t l 1 ) 0 0 3 2 1 6 0 0 3 3 1 6 p w m 1 h r e g i s t e r ( p w m 1 h ) pwm1l register (pwm1l)
3886 group user s manual application 2-107 2.6 pwm fig. 2.6.2 structure of port control register 1 2.6.2 relevant registers port control register 1 b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 p o r t c o n t r o l r e g i s t e r 1 ( p c t l 1 ) [ a d d r e s s 2 e 1 6 ] pwm 1 enable bit ? ? ? ? ? ? ? ? p 0 0 p 0 3 o u t p u t s t r u c t u r e s e l e c t i o n b i t 0 : p w m 0 o u t p u t d i s a b l e d 1 : p w m 0 o u t p u t e n a b l e d p 1 4 p 1 7 o u t p u t s t r u c t u r e s e l e c t i o n b i t 0: cmos 1: n-channel open-drain p 0 4 p 0 7 o u t p u t s t r u c t u r e s e l e c t i o n b i t p 1 0 p 1 3 o u t p u t s t r u c t u r e s e l e c t i o n b i t p 3 0 p 3 3 p u l l - u p c o n t r o l b i t p 3 4 p 3 7 p u l l - u p c o n t r o l b i t pwm 0 enable bit 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n 0 : n o p u l l - u p 1 : p u l l - u p 0 : n o p u l l - u p 1 : p u l l - u p 0: pwm 1 output disabled 1: pwm 1 output enabled
3886 group user s manual application 2-108 2.6 pwm fig. 2.6.3 structure of pwm0h register fig. 2.6.4 structure of pwm0l register pwm0h register b 7b 6b5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? p w m 0 h r e g i s t e r ( p w m 0 h ) [ a d d r e s s : 3 0 1 6 ] t h e h i g h - o r d e r 8 b i t s o f t h e p w m 0 h o u t p u t d a t a a r e s e t . a t w r i t i n g : a w r i t t e n d a t a i s t r a n s f e r r e d t o p w m 0 l a t c h a t e v e r y s u b - p e r i o d ( 6 4 s ) . ( f ( x i n ) = 8 m h z ) a t r e a d i n g : t h e c o n t e n t s o f t h e p w m 0 h r e g i s t e r a r e r e a d o u t . p w m 0 l r e g i s t e r b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t reset rw 0 1 2 3 4 6 7 ? ? ? pwm0l register (pwm0l) [address : 31 16 ] t h e l o w - o r d e r 6 b i t s o f t h e p w m 0 l o u t p u t d a t a a r e s e t . a t w r i t i n g : a w r i t t e n d a t a i s t r a n s f e r r e d t o p w m 0 l a t c h a t e v e r y r e p e t i t i v e p e r i o d ( 4 0 9 6 s ) . ( f ( x i n ) = 8 m h z ) a t r e a d i n g : t h e l o w - o r d e r 6 b i t s o f p w m 0 l a t c h a r e r e a d o u t . ? ? ? ? ? ? 5 ? nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . t h e c o m p l e t i o n o f t r a n s f e r t o t h e p w m 0 l a t c h i s i n d i c a t e d . 0 : t r a n s f e r c o m p l e t e d . 1 : n o t t r a n s f e r r e d . a t w r i t i n g : t h i s b i t i s s e t t o 1 .
3886 group user s manual application 2-109 2.6 pwm fig. 2.6.5 structure of pwm1h register fig. 2.6.6 structure of pwm1l register pwm1h register b 7b 6b5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? p w m 1 h r e g i s t e r ( p w m 1 h ) [ a d d r e s s : 3 2 1 6 ] t h e h i g h - o r d e r 8 b i t s o f t h e p w m 1 h o u t p u t d a t a a r e s e t . a t w r i t i n g : a w r i t t e n d a t a i s t r a n s f e r r e d t o p w m 1 l a t c h a t e v e r y s u b - p e r i o d ( 6 4 s ) . ( f ( x i n ) = 8 m h z ) a t r e a d i n g : t h e c o n t e n t s o f t h e p w m 1 h r e g i s t e r a r e r e a d o u t . p w m 1 l r e g i s t e r b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t reset rw 0 1 2 3 4 6 7 ? ? ? pwm1l register (pwm1l) [address : 33 16 ] t h e l o w - o r d e r 6 b i t s o f t h e p w m 1 l o u t p u t d a t a a r e s e t . a t w r i t i n g : a w r i t t e n d a t a i s t r a n s f e r r e d t o p w m 1 l a t c h a t e v e r y r e p e t i t i v e p e r i o d ( 4 0 9 6 s ) . ( f ( x i n ) = 8 m h z ) a t r e a d i n g : t h e l o w - o r d e r 6 b i t s o f p w m 1 l a t c h a r e r e a d o u t . ? ? ? ? ? ? 5 ? nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . t h e c o m p l e t i o n o f t r a n s f e r t o t h e p w m 1 l a t c h i s i n d i c a t e d . 0 : t r a n s f e r c o m p l e t e d . 1 : n o t t r a n s f e r r e d . a t w r i t i n g : t h i s b i t i s s e t t o 1 .
3886 group user s manual application 2-110 2.6 pwm fig. 2.6.7 structure of ad/da control register b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 1 0 0 0 ad/da control register (adcon) [address : 34 16 ] a d / d a c o n t r o l r e g i s t e r 0 0 0 0 : p6 0 /an 0 0 0 1 : p6 1 /an 1 0 1 0 : p6 2 /an 2 0 1 1 : p6 3 /an 3 1 0 0 : p6 4 /an 4 1 0 1 : p6 5 /an 5 1 1 0 : p6 6 /an 6 1 1 1 : p6 7 /an 7 a n a l o g i n p u t p i n s e l e c t i o n b i t s b 2 b 1 b 0 ad conversion completion bit 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d 0 p w m 0 o u t p u t p i n s e l e c t i o n b i t 0: p5 6 /pwm 01 1: p3 0 /pwm 00 p w m 1 o u t p u t p i n s e l e c t i o n b i t0 : p 5 7 / p w m 1 1 1 : p 3 1 / p w m 1 0 d a 1 o u t p u t e n a b l e b i t 0 : d a 1 o u t p u t d i s a b l e d 1 : d a 1 o u t p u t e n a b l e d da 2 output enable bit 0: da 2 output disabled 1: da 2 output enabled
3886 group user s manual application 2-111 2.6 pwm 2.6.3 pwm application example (1) control of vs tuner figure 2.6.8 shows a connection diagram, and figure 2.6.9 shows the setting of relevant registers. fig. 2.6.8 connection diagram p5 6 /da 1 /pwm 01 filter v t a n t 0 3 2 v v s t u n e r 3 8 8 6 g r o u p
3886 group user s manual application 2-112 2.6 pwm fig. 2.6.9 relevant registers setting outline: control of vs tuner by using the 14-bit resolution pwm 0 output function f(x in ) = 8 mhz p w m c o n t r o l r e g i s t e r 1 ( a d d r e s s 2 e 1 6 ) p c t l 1 1 enable pwm 0 output n o t e : t h e p w m 0 o u t p u t f u n c t i o n h a s p r i o r i t y e v e n w h e n t h e b i t c o r r e s p o n d i n g t o p 5 6 p i n of p o r t p 5 d i r e c t i o n r e g i s t e r i s s e t t o t h e i n p u t m o d e . p w m 0 h r e g i s t e r ( a d d r e s s 3 0 1 6 ) s e t hi g h - o r d e r 8 b i t s ( n ) o f 1 4 - b i t d a t a t o b e o u t p u t p w m 0 h n o t e : d e p e n d i n g o n d a t a ( n ) o f t h e h i g h - o r d e r 8 b i t s , t h e p e r i o d ( 2 5 0 ? n ) o f h l e v e l d u r i n g t h e s u b - p e r i o d ( 6 4 s ) i s d e t e r m i n e d . pwm0l register (address 31 16 ) set low-order 6 bits (m) of 14-bit data to be output p w m 0 l n o t e : d e p e n d i n g o n d a t a ( m ) o f t h e l o w - o r d e r 6 b i t s , t h e n u m b e r o f s u b - p e r i o d t o w h i c h t h e a d d b i t i s t o b e a d d e d w i t h i n t h e r e p e t i t i v e c y c l e c o n s i s t i n g o f 6 4 s u b - p e r i o d s i s d e t e r m i n e d . w h e n o u t p u t d a t a i s w r i t t e n t o t h e p w m 0 l r e g i s t e r , b i t 7 o f t h i s r e g i s t e r b e c o m e s 1 . w h e n c o m p l e t i n g t o t r a n s f e r d a t a f r o m t h e p w m 0 l r e g i s t e r t o t h e p w m 0 l a t c h , b i t 7 b e c o m e s 0 . ad/da control register (address 34 16 ) a dc o n 0 s e l e c t p 5 6 / p w m 0 1 o u t p u t p i n
3886 group user s manual application 2-113 2.6 pwm fig. 2.6.11 pwm 0 output control procedure: pwm waveform is output to the external by setting relevant registers shown figure 2.6.9. this pwm 0 output is integrated through the low pass filter and converted into dc signals for control of the vs tuner. figure 2.6.10 shows the control procedure. fig. 2.6.10 control procedure 2.6.4 notes on pwm for pwm 0 output, l level is output first. after data is set to the pwm0l and the pwm0h registers, pwm waveform corresponding to the new data is output from next repetitive period. p w m 0 h ( a d d r e s s 0 0 3 0 1 6 ) p w m 0 l ( a d d r e s s 0 0 3 1 1 6 ) d a t a t o b e o u t p u t after setting data, pwm waveform corresponding to the new data is output from the next repetitive period. p c t l 1 ( a d d r e s s 0 0 2 e 1 6 ) , b i t 6 1 p w m 0 e n a b l e d a dc o n ( a d d r e s s 0 0 3 4 1 6 ) , b i t 4 0 p 5 6 / d a 1 / p w m 0 1 p i n s e t a s t h e p w m o u t p u t p i n p w m 0 o u t p u t d a t a i s u p d a t e d . u p d a te d d a t a i s o u t p u t f r o m n e x t r e p e t i t i v e p e r i o d .
3886 group user? manual application 2.7 a-d converter 2.7 a-d converter this paragraph explains the registers setting method and the notes relevant to the a-d converter. 2.7.1 memory map fig. 2.7.1 memory map of registers relevant to a-d converter 2.7.2 relevant registers fig. 2.7.2 structure of ad/da control register 0 0 3 4 1 6 0035 16 0038 16 003d 16 a d / d a c o n t r o l r e g i s t e r ( a d c o n ) a-d conversion register 1 (ad1) a-d conversion register 2 (ad2) interrupt request register 2 (ireq2) 003f 16 interrupt control register 2 (icon2) 0 0 3 9 1 6 i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( i n t s e l ) b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 1 0 0 0 ad/da control register (adcon) [address : 34 16 ] a d / d a c o n t r o l r e g i s t e r 0 0 0 0 : p6 0 /an 0 0 0 1 : p6 1 /an 1 0 1 0 : p6 2 /an 2 0 1 1 : p6 3 /an 3 1 0 0 : p6 4 /an 4 1 0 1 : p6 5 /an 5 1 1 0 : p6 6 /an 6 1 1 1 : p6 7 /an 7 a n a l o g i n p u t p i n s e l e c t i o n b i t s b 2 b 1 b 0 ad conversion completion bit 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d 0 p w m 0 o u t p u t p i n s e l e c t i o n b i t0 : p 5 6 / p w m 0 1 1 : p 3 0 / p w m 0 0 pwm 1 output pin selection bit 0 : p 5 7 / p w m 1 1 1 : p 3 1 / p w m 1 0 d a 1 o u t p u t e n a b l e b i t0 : d a 1 o u t p u t d i s a b l e d 1 : d a 1 o u t p u t e n a b l e d d a 2 o u t p u t e n a b l e b i t0 : d a 2 o u t p u t d i s a b l e d 1 : d a 2 o u t p u t e n a b l e d
3886 group user s manual application 2-115 2.7 a-d converter fig. 2.7.3 structure of a-d conversion register 1 fig. 2.7.4 structure of a-d conversion register 2 a-d conversion register 1 b 7b 6b5b 4b 3b 2b 1b 0 b function a t reset rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 ) [ a d d r e s s : 3 5 1 6 ] t h e r e a d - o n l y r e g i s t e r i n w h i c h t h e a - d c o n v e r s i o n s r e s u l t s a r e s t o r e d . ? ? ? ? ? ? ? ? < 8-bit read> b 7 b8 b 7b 6b5b 4b3 b 0 b 2 b 9 < 10-bit read> b 7 b6 b5 b4 b3 b2 b1 b 0 b0 b7 a-d conversion register 2 b 7b 6b5b 4b 3b 2b 1b 0 b function a t reset rw 0 1 2 3 4 5 6 7 name ? ? 0 0 0 0 0 0 t h e r e a d - o n l y r e g i s t e r i n w h i c h t h e a - d c o n v e r s i o n s r e s u l t s a r e s t o r e d . ? ? ? ? ? ? ? < 10-bit read> b 7 b9 b 0 b 8 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . a - d c o n v e r s i o n r e g i s t e r 2 ( a d 2 ) [ a d d r e s s : 3 8 ] 16 c o n v e r s i o n m o d e s e l e c t i o n b i t 0 : 1 0 - b i t a - d m o d e 1 : 8 - b i t a - d m o d e
3886 group user s manual application 2.7 a-d converter fig. 2.7.5 structure of interrupt source selection register i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t s o u r c e s e l e c t i o n b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : int 0 interrupt 1 : input buffer full interrupt int2/i 2 c interrupt source selection bit cntr 1 /key-on wake-up interrupt source selection bit 0 : int 1 interrupt 1 : output buffer empty interrupt s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t c n t r 0 / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : serial i/o1 transmit interrupt 1 : s cl ,s da interrupt 0 : cntr 0 interrupt 1 : s cl ,s da interrupt s e r i a l i / o 2 / i 2 c i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : serial i/o2 interrupt 1 : i 2 c interrupt 0 : int 2 interrupt 1 : i 2 c interrupt 0 : cntr 1 interrupt 1 : key-on wake-up interrupt a d c o n v e r t e r / k e y - o n w a k e - u p i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : a-d converter interrupt 1 : key-on wake-up interrupt ? 1 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 2 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 3 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . interrupt source selection register (intsel) [address 39 16 ] ? 1 ? 2 ? 2 ? 3 ? 3 ? 1
3886 group user s manual application 2-117 2.7 a-d converter fig. 2.7.6 structure of interrupt request register 2 fig. 2.7.7 structure of interrupt control register 2 interrupt request register 2 b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s : 3 d 1 6 ] nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . ? c n t r 0 / s c l , s d a i n t e r r u p t r e q u e s t b i t c n t r 1 / k e y - o n w a k e - u p i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued int 4 interrupt request bit ad converter/key-on wake-up interrupt request bit ? : t h e s e b i t s c a n b e c l e a r e d t o 0 b y p r o g r a m , b u t c a n n o t b e s e t t o 1 . 0 : no interrupt request issued 1 : interrupt request issued s e r i a l i / o 2 / i 2 c i n t e r r u p t r e q u e s t b i t i n t 2 / i 2 c i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued i n t 3 i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? i n t e r r u p t c o n t r o l r e g i s t e r 2 b7 b6 b5 b4 b3 b2 b1 b0 b function a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] f i x t h i s b i t t o 0 . c n t r 0 / s c l , s d a i n t e r r u p t e n a b l e b i t cntr 1 /key-on wake-up interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled int 4 interrupt enable bit ad converter/key-on wake-up interrupt enable bit s e r i a l i / o 2 / i 2 c i n t e r r u p t e n a b l e b i t i n t 2 / i 2 c i n t e r r u p t e n a b l e b i t i n t 3 i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0
3886 group user s manual application 2.7 a-d converter 2.7.3 a-d converter application examples (1) conversion of analog input voltage outline : the analog input voltage input from a sensor is converted to digital values. figure 2.7.8 shows a connection diagram, and figure 2.7.9 shows the relevant registers setting. fig. 2.7.8 connection diagram specifications : the analog input voltage input from a sensor is converted to digital values. p6 0 /an 0 pin is used as an analog input pin. fig. 2.7.9 relevant registers setting p 6 0 / a n 0 3886 group s e n s o r ad/da control register (address 34 1 6 ) adcon 0 a n a l o g i n p u t p i n : p 6 0 / a n 0 s e l e c t e d a - d c o n v e r s i o n s t a r t 0 0 b 0 b 7 a - d c o n v e r s i o n r e g i s t e r 2 ( a d d r e s s 3 8 1 6 ) a d 2 ad1 b 0 b 7 b 0 b 7 (read-only) a-d conversion register 1 (address 35 16 ) ( r e a d - o n l y ) a r e s u l t o f a - d c o n v e r s i o n i s s t o r e d ( n o t e ) . note : after bit 3 of adcon is set to 1 , read out that contents. when reading 10-bit data, read address 0038 16 before address 0035 16 ; when reading 8-bit data, read address 0035 16 only. when reading 10-bit data, bits 2 to 6 of address 0038 16 are 0 . 0
3886 group user s manual application 2-119 2.7 a-d converter an analog input signal from a sensor is converted to the digital value according to the relevant registers setting shown by figure 2.7.9. figure 2.7.10 shows the control procedure for 8-bit read, and figure 2.7.11 shows the control procedure for 10-bit read. fig. 2.7.10 control procedure for 8-bit read fig. 2.7.11 control procedure for 10-bit read a d c o n ( a d d r e s s 3 4 1 6 ) x x x x 0 0 0 0 2 r e a d o u t a d 1 ( a d d r e s s 3 5 1 6 ) a d c o n ( a d d r e s s 3 4 1 6 ) , b i t 3 ? 1 0 p 6 0 / a n 0 p i n s e l e c t e d a s a n a l o g i n p u t p i n a - d c o n v e r s i o n s t a r t j u d g m e n t o f a - d c o n v e r s i o n c o m p l e t i o n read out of conversion resul t x : t h i s b i t i s n o t u s e d h e r e . s e t i t t o 0 o r 1 a r b i t r a r i l y . a d c o n ( a d d r e s s 3 4 1 6 ) xxxx0000 2 read out ad2 (address 38 16 ) a d c o n ( a d d r e s s 3 4 1 6 ) , b i t 3 ? 1 0 p6 0 /an 0 pin selected as analog input pin a-d conversion start judgment of a-d conversion completion read out of high-order digit (b9, b8) of conversion result read out ad1 (address 35 16 ) read out of low-order digit (b7 b0) of conversion result x: this bit is not used here. set it to 0 or 1 arbitrarily.
3886 group user s manual application 2.7 a-d converter 2.7.4 notes on a-d converter (1) analog input pin make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 f to 1 f. further, be sure to verify the operation of application products on the user side. reason an analog input pin includes the capacitor for analog voltage comparison. accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. this may cause the a-d conversion precision to be worse. (2) a-d converter power source pin the av ss pin is an a-d converter power source pin. regardless of using the a-d conversion function or not, connect them as following : av ss : connect to the v ss line reason if the av ss pin id opened, the microcomputer may have a failure because of noise or others. (3) clock frequency during a-d conversion the comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. thus, make sure the following during an a-d conversion. f(x in ) is 500 khz or more do not execute the stp instruction
3886 group user? manual application 2-121 2.8 d-a converter 2.8 d-a converter this paragraph explains the registers setting method and the notes relevant to the d-a converter. 2.8.1 memory map fig. 2.8.1 memory map of registers relevant to d-a converter d-a2 conversion register (da2) d-a1 conversion register (da1) 0037 16 0036 16 ad/da control register (adcon) 0034 16 port p5 direction register (p5d) 000b 16
3886 group user s manual application 2.8 d-a converter 2-122 2.8.2 relevant registers fig. 2.8.2 structure of port p5 direction register fig. 2.8.3 structure of ad/da control register port p5 direction register b7 b6 b5 b4 b3 b2 b1 b0 port p5 direction register (p5d: address 0b 16 ) 0 : port p5 0 input mode 1 : port p5 0 output mode b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0 0 : port p5 2 input mode 1 : port p5 2 output mode 0 0 : port p5 3 input mode 1 : port p5 3 output mode 0 0 : port p5 4 input mode 1 : port p5 4 output mode 0 0 : port p5 5 input mode 1 : port p5 5 output mode 0 0 : port p5 6 input mode 1 : port p5 6 output mode 0 0 : port p5 7 input mode 1 : port p5 7 output mode 0 port p5 direction register 0 : port p5 1 input mode 1 : port p5 1 output mode ad/da control register b7 b6 b5 b4 b3 b2 b1 b0 ad/da control register (adcon: address 34 16 ) b 0 1 2 name 0 functions at reset r w 0 0 1 analog input pin selection bits b2 b1 b0 0 0 0: p6 0 /an 0 0 0 1: p6 1 /an 1 0 1 0: p6 2 /an 2 0 1 1: p6 3 /an 3 1 0 0: p6 4 /an 4 1 0 1: p6 5 /an 5 1 1 0: p6 6 /an 6 1 1 1: p6 7 /an 7 3 0 pwm 0 output pin selection bit 0: p5 6 /pwm 01 1: p3 0 /pwm 00 ad conversion completion bit 0: conversion in progress 1: conversion completed 4 0 5 0 da 1 output enable bit 0: da 1 output disabled 1: da 1 output enabled 0 da 2 output enable bit 0: da 2 output disabled 1: da 2 output enabled 6 7 pwm 1 output pin selection bit 0: p5 7 /pwm 11 1: p3 1 /pwm 10
3886 group user s manual application 2-123 2.8 d-a converter fig. 2.8.4 structure of d-ai converter register d-ai conversion register b7 b6 b5 b4 b3 b2 b1 b0 d-ai conversion register (i = 1, 2) (dai: addresses 36 16 , 37 16 ) b 0 0 0 0 0 0 0 0 at reset r w 1 2 3 4 5 6 7 functions this is d-a output value stored bits. this is write exclusive register. 0 0 0 0 0 0 0 0
3886 group user s manual application 2.8 d-a converter 2-124 2.8.3 d-a converter application example (1) speaker output volume modulation outline: the volume of a speaker output is modulated by using d-a converter. specifications: timer x modulates the period of sound for the pitch interval, so that a fixed pitch ( la : approx. 440 hz) can be output. modulating the amplitude with the d-a output value controls the volume. use f(x in ) = 6 mhz. use da1 (p5 6 /da 1 pin) as d-a converter. figure 2.8.5 shows a peripheral circuit example and figure 2.8.6 shows a speaker output example. figure 2.8.7 shows the relevant registers setting. fig. 2.8.5 peripheral circuit example fig. 2.8.6 speaker output example amplification circuit power amplifier 3886 group + p5 6 /da 1 v ref v ss timer x interrupt timer x interrupt timer x interrupt timer x interrupt timer x interrupt timer x interrupt modulation of volume (amplitude is set by d-a 1 output) modulation of pitch interval: 440 hz (cycle is set by timer x)
3886 group user s manual application 2-125 2.8 d-a converter fig. 2.8.7 relevant registers setting b7 b0 port p5 direction register (p5d) (address 0b 16 ) p5 6 /da 1 : input mode d-a1 conversion register (da1) (address 36 16 ) timer xy mode register (tm) (address 23 16 ) set conversion value (n) 0 b7 b0 b7 b0 ad/da control register (adcon) (address 34 16 ) da 1 output enabled 1 b7 b0 1 0 0 timer x count: stop timer mode prescaler x (prex) (address 24 16 ) b7 b0 01 16 set division ratio 1 timer x (tx) (address 25 16 ) b7 b0 d6 16 set division ratio 1 b7 b0 interrupt request register 1 (ireq1) (address 3c 16 ) timer x interrupt request 0 b7 b0 interrupt control register 1 (icon1) (address 3e 16 ) timer x interrupt: enabled 1 timer xy mode register (tm) (address 23 16 ) b7 b0 0 timer x count: start 0 0 analog voltage v = vref n 256 (n=0 to 255)
3886 group user s manual application 2.8 d-a converter 2-126 when the registers are set as shown in figure 2.8.7, the speaker output volume is modulated by the d-a output value. figure 2.8.8 shows the control procedure. fig. 2.8.8 control procedure r e s e t i n i t i a l i z a t i o n s e i c l t ( n o t e 1 ) c l d ( n o t e 2 ) i c o n 1 p 5 d a d c o n t m p r e x t x w o r k f l a g ( n o t e 3 ) i r e q 1 i c o n 1 d a 1 c l i t m 0 0 2 1 d 6 1 6 1 main processing value of work flag ? 1 0 r t i ( a d d r e s s 3 e 1 6 ) , b i t 4 ( a d d r e s s 0 b 1 6 ) , b i t 6 ( a d d r e s s 3 4 1 6 ) ( a d d r e s s 2 3 1 6 ) ( a d d r e s s 2 4 1 6 ) ( a d d r e s s 2 5 1 6 ) ( a d d r e s s 3 c 1 6 ) , b i t 4 ( a d d r e s s 3 e 1 6 ) , b i t 4 ( a d d r e s s 3 6 1 6 ) ( a d d r e s s 2 3 1 6 ) 0 1 . . . . . t i m e r x i n t e r r u p t p r o c e s s r o u t i n e pop registers x 1 x x x x x x 2 all interrupts disabled timer x interrupt disabled set port p5 6 to input mode da1 output enabled timer y: timer mode, timer x count: stop set division ratio 1 to prescaler x set division ratio 1 to timer x timer x interrupt request bit cleared timer x interrupt: enabled d-a converter start all interrupts enabled timer x count start notes 1 : when using index x mode flag 2: when using decimal mode flag 3: the work flag is a user flag for work. when this flag is 1 , a value other than vss is output from the da output pin. when this flag is 0 , vss is output from the da output pin. push registers used in interrupt process routine pop registers pushed to stac k x: this bit is not used here. set it to 0 or 1 arbitrarily. x x 0 0 1 x x x 2 . . . . . 1 s e t o u t p u t v a l u e ( v o l u m e ) x x 0 0 0 x x x 2 p u s h r e g i s t e r s t o s t a c k set value except vss to d-a1 conversion register. set 0 to work flag. set value of vss to d-a1 conversion register. set 1 to work flag.
3886 group user s manual application 2-127 2.8 d-a converter 2.8.4 notes on d-a converter (1) vcc when using d-a converter the d-a converter accuracy when vcc is 4.0 v or less differs from that of when vcc is 4.0 v or more. when using the d-a converter, we recommend using a vcc of 4.0 v or more. (2) d-ai conversion register when not using d-a converter when a d-a converter is not used, set all values of the d-ai conversion registers (i = 1, 2) to 00 16 . the initial value after reset is 00 16 .
3886 group user? manual application 2.9 bus interface 2.9 bus interface this paragraph explains the registers setting method and the programming examples relevant to the bus interface. 2.9.1 memory map fig. 2.9.1 memory map of registers relevant to bus interface 0028 16 0 0 2 9 1 6 data bus buffer register 0 (dbb0) d a t a b u s b u f f e r s t a t u s r e g i s t e r 0 ( d b b s t s 0 ) 002a 16 data bus buffer control register (dbbcon) 0 0 2 b 1 6 d a t a b u s b u f f e r r e g i s t e r 1 ( d b b 1 ) 0 0 2 c 1 6 d a t a b u s b u f f e r s t a t u s r e g i s t e r 1 ( d b b s t s 1 ) 0 0 3 9 1 6 i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( i n t s e l ) 003c 16 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) 003e 16 interrupt control register 1 (icon1) 0 0 2 f 1 6 p o r t c o n t r o l r e g i s t e r 2 ( p c t l 2 )
3886 group user s manual application 2-129 2.9 bus interface fig. 2.9.2 structure of data bus buffer register i 2.9.2 relevant registers fig. 2.9.3 structure of data bus buffer status register i d a t a b u s b u f f e r r e g i s t e r i b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t reset rw 0 1 2 3 4 5 6 7 n a m e ? ? ? ? ? ? ? ? d a t a b u s b u f f e r r e g i s t e r i ( d b b i ) ( i = 0 , 1 ) [ a d d r e s s : 2 8 1 6 / 2 b 1 6 ] b u f f e r r e g i s t e r t o w r i t e o u t p u t d a t a a n d r e a d i n p u t d a t a . a t w r i t e : d a t a i s w r i t t e n t o o u t p u t d a t a b u f f e r r e g i s t e r . a t r e a d : t h e c o n t e n t s o f i n p u t d a t a b u f f e r r e g i s t e r a r e r e a d o u t . note: output data bus buffer and input data bus buffer are assigned to the same address. the contents of output data bus buffer register cannot be read out. writing to input data bus buffer register is disabled. 7 d a t a b u s b u f f e r s t a t u s r e g i s t e r i b 7b 6b5b 4b 3b 2b 1b 0 b function a t reset rw 0 1 2 3 4 name 0 0 0 0 0 o u t p u t b u f f e r f u l l f l a g i i n p u t b u f f e r f u l l f l a g i 0 : buffer empty 1 : buffer full u s e r d e f i n a b l e f l a g s ( t h i s f l a g c a n b e d e f i n e d b y u s e r f r e e l y . ) a 0 i f l a g u s e r d e f i n a b l e f l a g s ( t h i s f l a g c a n b e d e f i n e d b y u s e r f r e e l y . ) 0 : buffer empty 1 : buffer full this flag indicates the condition of a 0i status when the ibf i flag is set. data bus buffer status register i (dbbstsi) (i=0, 1) [address 29 16 /2c 16 ] 50 60 0 ? ? ?
3886 group user s manual application 2.9 bus interface fig. 2.9.4 structure of data bus buffer control register fig. 2.9.5 structure of interrupt source selection register 0 : p4 2 functions as port i/o pin. 1 : p4 2 functions as obf 00 output pin. data bus buffer control register b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 d a t a b u s b u f f e r c o n t r o l r e g i s t e r ( d b b c o n ) [ a d d r e s s 2 a 1 6 ] fix this bit to 0 . d a t a b u s b u f f e r e n a b l e b i t d a t a b u s b u f f e r f u n c t i o n s e l e c t i o n b i t 0 : p5 0 p5 3 , p8 i/o port 1 : data bus buffer enabled o b f 1 0 o u t p u t e n a b l e b i t i n p u t l e v e l s e l e c t i o n b i t o b f 0 o u t p u t s e l e c t i o n b i t o b f 0 0 o u t p u t e n a b l e b i t obf 01 output enable bit 0 : single data bus buffer mode (p4 7 functions as i/o port.) 1 : double data bus buffer mode (p4 7 functions as s 1 input.) 0 : obf 00 valid 1 : obf 01 valid 0 : p4 3 functions as port i/o pin. 1 : p4 3 functions as obf 01 output pin. 0 : p4 6 functions as port i/o pin. 1 : p4 6 functions as obf 10 output pin. 0 : cmos level input 1 : ttl level input i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r b 7b 6b5b 4b 3b 2b 1b 0 b function a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 int 0 /input buffer full interrupt source selection bit i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : int 0 interrupt 1 : input buffer full interrupt i n t 2 / i 2 c i n t e r r u p t s o u r c e s e l e c t i o n b i t c n t r 1 / k e y - o n w a k e - u p i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : int 1 interrupt 1 : output buffer empty interrupt s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t c n t r 0 / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : serial i/o1 transmit interrupt 1 : s cl ,s da interrupt 0 : cntr 0 interrupt 1 : s cl ,s da interrupt s e r i a l i / o 2 / i 2 c i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : serial i/o2 interrupt 1 : i 2 c interrupt 0 : int 2 interrupt 1 : i 2 c interrupt 0 : cntr 1 interrupt 1 : key-on wake-up interrupt a d c o n v e r t e r / k e y - o n w a k e - u p i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : a-d converter interrupt 1 : key-on wake-up interrupt ? 1 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 2 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 3 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . interrupt source selection register (intsel) [address 39 16 ] ? 1 ? 2 ? 2 ? 3 ? 3 ? 1
3886 group user s manual application 2-131 2.9 bus interface fig. 2.9.6 structure of interrupt request register 1 fig. 2.9.7 structure of interrupt control register 1 interrupt request register 1 b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s : 3 c 1 6 ] i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t r e q u e s t b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued timer y interrupt request bit timer 1 interrupt request bit ? : t h e s e b i t s c a n b e c l e a r e d t o 0 b y p r o g r a m , b u t c a n n o t b e s e t t o 1 . 0 : no interrupt request issued 1 : interrupt request issued s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued t i m e r x i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? t i m e r 2 i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued ? i n t e r r u p t c o n t r o l r e g i s t e r 1 b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s : 3 e 1 6 ] i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t e n a b l e b i t int 1 /output buffer empty interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled t i m e r y i n t e r r u p t e n a b l e b i t timer 1 interrupt enable bit s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled t i m e r 2 i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled
3886 group user s manual application 2.9 bus interface p o r t c o n t r o l r e g i s t e r 2 b 7b 6b5b 4b 3b 2b 1b 0 b function a t reset rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 p o r t c o n t r o l r e g i s t e r 2 ( p c t l 2 ) [ a d d r e s s 2 f 1 6 ] p o r t o u t p u t p 4 2 / p 4 3 c l e a r f u n c t i o n s e l e c t i o n b i t p 4 i n p u t l e v e l s e l e c t i o n b i t ( p 4 2 p 4 6 ) 0 : a u t o m a t i c s e t 0 1 1 6 t o t i m e r 1 a n d f f 1 6 t o p r e s c a l e r 1 2 1 : n o a u t o m a t i c s e t p 8 f u n c t i o n s e l e c t i o n b i t 0 : c m o s l e v e l i n p u t 1 : t t l l e v e l i n p u t p 7 i n p u t l e v e l s e l e c t i o n b i t ( p 7 0 p 7 5 ) p 4 o u t p u t s t r u c t u r e s e l e c t i o n b i t ( p 4 2 , p 4 3 , p 4 4 , p 4 6 ) i n t 2 , i n t 3 , i n t 4 i n t e r r u p t s w i t c h b i t t i m e r y c o u n t s o u r c e s e l e c t i o n b i t o s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r s t p i n s t r u c t i o n r e l e a s e d b i t 0 : c m o s l e v e l i n p u t 1 : t t l l e v e l i n p u t 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n 0 : p o r t p 8 / p o r t p 8 d i r e c t i o n r e g i s t e r 1 : p o r t p 4 i n p u t r e g i s t e r / p o r t p 7 i n p u t r e g i s t e r 0 : i n t 2 0 , i n t 3 0 , i n t 4 0 i n t e r r u p t 1 : i n t 2 1 , i n t 3 1 , i n t 4 1 i n t e r r u p t 0 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) 1 : f ( x c i n ) 0 : o n l y s o f t w a r e c l e a r 1 : s o f t w a r e c l e a r a n d o u t p u t d a t a b u s b u f f e r 0 r e a d i n g ( s y s t e m b u s s i d e ) ? ? ? ? ? ? ? ? fig. 2.9.8 structure of port control register 2
3886 group user s manual application 2-133 2.9 bus interface 2.9.3 bus interface overview the 3886 group has the built-in bus interface of two bytes to activate itself as a slave microcomputer. a slave microcomputer is the microcomputer which is operated owing to the host cpu s indication. data is asynchronously transmitted/received between the host cpu and the slave microcomputer, through the bus interface of these two bytes. accordingly, the slave microcomputer can be treated as well as two general peripheral lsis on the host cpu side. consequently, it is easy to change its function by updating the slave s program. the performance overview of 3886 group s built-in bus interface is as follows: 8-bit data bus built-in data bus buffer of two levels for input and output each possible externally to output input/output buffer state as status. figure 2.9.9 shows the bus interface block diagram. fig. 2.9.9 bus interface block diagram host cpu dbb1 dbb2 s l a v e c p u 3 8 8 6 g r o u p data bus data bus
3886 group user s manual application 2.9 bus interface 2.9.4 input/output operation (1) input operation the bus interface input operation is explained as the following: ? when the logical or of si (i = 0, 1) and w is 0 , the data bus status is latched into the data bus buffer register i (dbbi) at the rising of w input signal. ? when the data is latched into the input data bus buffer register i, the ibfi flag of the data bus buffer status register i is simultaneously set to 1 . ? when the ibfi flag is set to 1 , the input buffer full interrupt request occurs and the input buffer full interrupt request bit is set to 1 . ? at the timing ? , the a0 level is stored into bit 3 of the data bus buffer status register i. bit 3 indicates that the contents of the input data bus buffer register i are data or a command. (2) output operation the bus interface output operation is explained as the following: ? writing data to the dbbi sets the obfi flag of the data bus status register i to 1 . ? when the logical or of si, r and a0 is 0 , the contents of the output data bus buffer register i are output on the system bus and the obfi flag is simultaneously cleared to 0 . ? at the rising of the r input signal, the output buffer empty interrupt request occurs and the output buffer empty interrupt request bit is set to 1 . si r w a0 data bus status data on data bus 0 0 1 0 read output data 0 0 1 1 read status information 0 1 0 0 write input data (data) 0 1 0 1 write input data (command) 1 ??? high impedance table 2.9.1 bus control signals and data bus status
3886 group user s manual application 2-135 2.9 bus interface 2.9.5 relevant registers setting figure 2.9.10 shows the relevant registers setting. fig. 2.9.10 relevant registers setting data bus buffer control register (address 2a 1 6 ) d b b c o n1 enable data bus buffer b 0 b 7 d a t a b u s b u f f e r s t a t u s r e g i s t e r 0 ( a d d r e s s 2 9 1 6 ) d b b s t s 0 b 0 b 7 0 0 1 interrupt source selection register (address 39 16 ) i n t s e l 1 b 0 b 7 1 d b b 0 b 0 b 7 dbbsts 0 b 0 b 7 d b b 0 b 0 b 7 0 select single data bus buffer mode validate obf 00 set p4 2 to obf 00 pin select input buffer full interrupt select output buffer empty interrupt < input > ? the condition of a0 0 status is stored. d a t a b u s b u f f e r r e g i s t e r 0 ( a d d r e s s 2 8 1 6 ) input data is stored ( note ). note: when the condition of a0 0 status is 0 , this is treated as data. when the condition is 1 , this is treated as a command. data bus buffer status register 0 (address 29 16 ) < output > confirm that the buffer is empty ( note ). data bus buffer register 0 (address 28 16 ) write output data. note: when using the output buffer empty interrupt, it is unnecessary to check the output buffer full flag 0.
3886 group user s manual application 2.9 bus interface figure 2.9.11 shows the control procedure using the interrupt. fig. 2.9.11 control procedure using interrupt dbbcon (address 2a 16 ) x x x x 1 0 0 1 2 r e a d o u t d b b 0 ( a d d r e s s 2 8 1 6 ) a s c o m m a n d dbbsts0 (address 29 16 ), bit3 ? 1 0 intsel (address 39 16 ) x x x x x x 1 1 2 read out dbbsts0 (address 29 16 ) write data to dbb0(address 28 16 ) d a t a b u s b u f f e r e n a b l e d s i n g l e d a t a b u s b u f f e r m o d e s e l e c t e d o b f 0 0 v a l i d a t e d ( p 4 2 o u t p u t ) i n p u t b u f f e r f u l l i n t e r r u p t s o u r c e s e l e c t e d o u t p u t b u f f e r e m p t y i n t e r r u p t s o u r c e s e l e c t e d < i n p u t > < output > r e a d o u t d b b 0 ( a d d r e s s 2 8 1 6 ) a s d a t a x : t h i s b i t i s n o t u s e d h e r e . s e t i t t o 0 o r 1 a r b i t r a r i l y .
3886 group user? manual application 2-137 2.10 watchdog timer 2.10 watchdog timer this paragraph explains the registers setting method and the notes relevant to the watchdog timer. 2.10.1 memory map fig. 2.10.1 memory map of registers relevant to watchdog timer 2.10.2 relevant registers fig. 2.10.2 structure of watchdog timer control register 001e 1 6 watchdog timer control register (wdtcon) 0 0 3 b 1 6 c p u m o d e r e g i s t e r ( c p u m ) watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 b function a t reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 0 0 watchdog timer control register (wdtcon) [address : 1e 16 ] w a t c h d o g t i m e r h ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t s ) s t p i n s t r u c t i o n d i s a b l e b i t 0 : s t p i n s t r u c t i o n e n a b l e d 1 : s t p i n s t r u c t i o n d i s a b l e d w a t c h d o g t i m e r h c o u n t s o u r c e s e l e c t i o n b i t 0 : w a t c h d o g t i m e r l u n d e r f l o w 1 : f ( x i n ) / 1 6 o r f ( x c i n ) / 1 6 ? ? ? ? ? ?
3886 group user s manual application 2.10 watchdog timer fig. 2.10.3 structure of cpu mode register cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 cpu mode register (cpum: address 3b 16 ) 00 : single-chip mode 01 : memory expansion mode (note) 10 : microprocessor mode (note) 11 : not available b 0 1 1 2 3 4 5 6 7 name 0 functions at reset r w 0 : 0 page 1 : 1 page 0 1 0 0: oscillating 1: stopped 0 1 0 processor mode bits stack page selection bit port xc switch bit fix this bit to 1 . main clock (x in - x out ) stop bit main clock division ratio selection bits * : the initial value of bit 1 depends on the cnvss level. note: this mode is not available for m3886 9m8a/mca/mfa or the flash memory version. b1 b0 b7 b6 0 0: =f(x in )/2 (high-speed mode) 0 1: =f(x in )/8 (middle-speed mode) 1 0: =f(x cin )/2 (low-speed mode) 1 1: not available 0: i/o port function (oscillation stopped) 1: x cin -x cout oscillation function *
3886 group user s manual application 2-139 2.10 watchdog timer 2.10.3 watchdog timer application examples (1) detection of program runaway outline : if program runaway occurs, let the microcomputer reset, using the internal timer for detection of program runaway. specifications : an underflow of watchdog timer h is judged to be program runaway, and the microcomputer is returned to the reset status. before the watchdog timer h underflows, 0 is set into bit 7 of the watchdog timer control register at every cycle in a main routine. high-speed mode is used as a main clock division ratio. an underflow signal of the watchdog timer l is supplied as the count source of watchdog timer h. figure 2.10.4 shows a watchdog timer connection and division ratio setting; figure 2.10.5 shows the relevant registers setting; figure 2.10.6 shows the control procedure. fig. 2.10.4 watchdog timer connection and division ratio setting f(x in ) = 8 mh z 1 / 1 6 1 / 2 5 6 1/256 reset fixed w a t c h d o g t i m e r lw a t c h d o g t i m e r h stp instruction disable bi t s t p i n s t r u c t i o n reset circuit internal reset
3886 group user s manual application 2.10 watchdog timer fig. 2.10.6 control procedure fig. 2.10.5 relevant registers setting 2.10.4 notes on watchdog timer make sure that the watchdog timer does not underflow while waiting stop release, because the watchdog timer keeps counting during that term. when the stp instruction disable bit has been set to 1 , it is impossible to switch it to 0 by a program. c p u m0 b 0 b 7 0 0 0 wdtcon 1 b 0 b 7 0 0 0 c p u m o d e r e g i s t e r ( a d d r e s s 3 b 1 6 ) processor mode: single-chip mode main clock (x in -x out ): operating main clock division ratio: f(x in )/2 (high-speed mode) watchdog timer h (for read-out of high-order 6 bits) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( a d d r e s s 1 e 1 6 ) enable stp instruction watchdog timer h count source: watchdog timer l underflow initialization sei clt cld cpum (address 3b 16 ) : : cli 000xxx00 2 wdtcon (address 1e 16 ), bit7,bit6 00 2 reset main processing : : a l l i n t e r r u p t s d i s a b l e d p r o c e s s o r m o d e : s i n g l e - c h i p m o d e m a i n c l o c k f ( x i n ) : o p e r a t i n g h i g h - s p e e d m o d e s e l e c t e d a s m a i n c l o c k d i v i s i o n r a t i o i n t e r r u p t s e n a b l e d w a t c h d o g t i m e r l u n d e r f l o w s e l e c t e d a s w a t c h d o g t i m e r h c o u n t s o u r c e s t p i n s t r u c t i o n e n a b l e d
3886 group user? manual 2-141 application 2.11 reset 2.11 reset 2.11.1 connection example of reset ic fig. 2.11.1 example of poweron reset circuit figure 2.11.2 shows the system example which switches to the ram backup mode by detecting a drop of the system power source voltage with the int interrupt. fig. 2.11.2 ram backup system v c c reset v s s m 6 2 0 2 2 l gnd 1 3 4 5 0.1 f p o w e r s o u r c e o u t p u t d e l a y c a p a c i t y 3 8 8 6 g r o u p v cc r e s e t 1 5 reset int cd v cc 1 v c c 2 v 1 gnd 2 6 3 7 m 6 2 0 0 9 l , m 6 2 0 0 9 p , m 6 2 0 0 9 f p 4 int v ss system power source voltage +5 v + 3886 group
3886 group user s manual 2.11 reset 2.11.2 notes on reset pin connecting capacitor in case where the reset signal rise time is long, connect a ceramic capacitor or others across the reset pin and the v ss pin. use a 1000 pf or more capacitor for high frequency use. when connecting the capacitor, note the following : make the length of the wiring which is connected to a capacitor as short as possible. be sure to verify the operation of application products on the user side. reason if the several nanosecond or several ten nanosecond impulse noise enters the reset pin, it may cause a microcomputer failure.
3886 group user? manual application 2-143 2.12 clock generating circuit 2.12 clock generating circuit this paragraph explains how to set the registers relevant to the clock generating circuit and describes an application example. 2.12.1 relevant registers fig. 2.12.1 structure of cpu mode register cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 cpu mode register (cpum: address 3b 16 ) 00 : single-chip mode 01 : memory expansion mode (note) 10 : microprocessor mode (note) 11 : not available b 0 1 1 2 3 4 5 6 7 name 0 functions at reset r w 0 : 0 page 1 : 1 page 0 1 0 0: oscillating 1: stopped 0 1 0 processor mode bits stack page selection bit port xc switch bit fix this bit to 1 . main clock (x in - x out ) stop bit main clock division ratio selection bits * : the initial value of bit 1 depends on the cnvss level. note: this mode is not available for m3886 9m8a/mca/mfa or the flash memory version. b1 b0 b7 b6 0 0: =f(x in )/2 (high-speed mode) 0 1: =f(x in )/8 (middle-speed mode) 1 0: =f(x cin )/2 (low-speed mode) 1 1: not available 0: i/o port function (oscillation stopped) 1: x cin -x cout oscillation function *
3886 group user s manual application 2.12 clock generating circuit 2-144 2.12.2 clock generating circuit application example (1) status transition during power failure outline: the clock counts up every second by using the timer interrupt during a power failure. fig. 2.12.2 connection diagram specifications: reducing power dissipation as low as possible while maintaining clock function clock: f(x in ) = 8 mhz, f(x cin ) = 32.768 khz port processing input port: fixed to h or l level externally. output port: fixed to output level that does not cause current flow to the external. (example) fix to h for an led circuit that turns on at l output level. i/o port: input port fixed to h or l level externally. output port output of data that does not consume current v ref pin: terminate a-d conversion operation stop v ref current dissipation by setting value of d-ai conversion register to 00 16 . figure 2.12.3 shows the status transition diagram during power failure and figure 2.12.4 shows the setting of relevant registers. fig. 2.12.3 status transition diagram during power failure 3886 group input port (note) power failure detection signal note: a signal is detected when input to input port, interrupt input pin, or analog input pin. reset released power failure detected internal system clock x cin x in middle-speed mode high-speed mode low-speed mode change internal system clock to high-speed mode after detection, change internal system clock to low-speed mode and stop oscillating x in -x out x cin -x cout oscillation function selected
3886 group user s manual application 2-145 2.12 clock generating circuit fig. 2.12.4 setting of relevant registers b7 b0 cpu mode register (cpum) (address 3b 16 ) main clock: high-speed mode (f(x in )/2) (note 1) 0 b7 b0 cpum 00 0100 cpum 0 01 0100 cpu mode register (cpum) (address 3b 16 ) port x c : x cin x cout oscillation function (note 2) b7 b0 10 0 internal system clock: low-speed mode (f(x cin )/2) cpum cpu mode register (cpum) (address 3b 16 ) 11 0 0 b7 b0 10 cpum cpu mode register (cpum) (address 3b 16 ) 11 0 0 1 main clock f(x in ): stopped notes 1: this setting is necessary only when selecting the high-speed mode. 2: when selecting the middle-speed mode, bit 6 is 1 .
3886 group user s manual application 2.12 clock generating circuit 2-146 fig. 2.12.5 control procedure control procedure: to prepare for a power failure, set the relevant registers in the order shown below. i n i t i a l i z a t i o n c p u m ( a d d r e s s 3 b 1 6 ) , b i t 7 , b i t 6 c p u m ( a d d r e s s 3 b 1 6 ) , b i t 4 0 , 0 1 c p u m ( a d d r e s s 3 b 1 6 ) , b i t 7 , b i t 6 c p u m ( a d d r e s s 3 b 1 6 ) , b i t 5 1, 0 (note) 1 (note) reset i n t e r n a l s y s t e m c l o c k : f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) m a i n c l o c k f ( x i n ) o s c i l l a t i o n s t o p p e d note: do not switch simultaneously. r e t u r n p r o c e s s i n g f r o m p o w e r f a i l u r e s e t t i m e r i n t e r r u p t t o o c c u r s e v e r y s e c o n d . e x e c u t e w i t i n s t r u c t i o n . a t p o w e r f a i l u r e , c l o c k c o u n t i s p e r f o r m e d d u r i n g t i m e r i n t e r r u p t p r o c e s s i n g ( e v e r y s e c o n d ) . port x c : x cin -x cout oscillation function when selecting main clock f(x in )/2 (high-speed mode) d e t e c t p o w e r f a i l u r e ? n y r e t u r n c o n d i t i o n f r o m p o w e r f a i l u r e c o m p l e t e d ? n y x: this bit is not used here. set it to 0 or 1 arbitrarily.
3886 group user? manual application 2-147 2.13 standby function 2.13 standby function the 3886 group is provided with standby functions to stop the cpu by software and put the cpu into the low-power operation. the following two types of standby functions are available. ?top mode using stp instruction ?ait mode using wit instruction 2.13.1 stop mode the stop mode is set by executing the stp instruction. in the stop mode, the oscillation of both clocks (x in x out , x cin ? cout ) stop and the internal clock stops at the ??level. the cpu stops and peripheral units stop operating. as a result, power dissipation is reduced. (1) state in stop mode table 2.13.1 shows the state in the stop mode. table 2.13.1 state in stop mode item oscillation cpu internal clock i/o ports p0?8 timer pwm0, pwm1 watchdog timer serial i/o1, serial i/o2 i 2 c-bus interface a-d converter d-a converter comparator bus interface state in stop mode stopped. stopped. stopped at ??level. retains the state at the stp instruction execution. stopped. (timers 1, 2, x, y) however, timers x and y can be operated in the event counter mode. stopped. stopped. stopped. however, these can be operated only when an external clock is selected. stopped. stopped. retains output voltage. stopped. operating.
3886 group user? manual application 2.13 standby function 2-148 (2) release of stop mode the stop mode is released by a reset input or by the occurrence of an interrupt request. note the differences in the restoration process according to reset input or interrupt request, as described below. restoration by reset input the stop mode is released by holding the reset pin to the ??input level during the stop mode. oscillation is started when all ports are in the input state and the stop mode of the main clock (x in - x out ) is released. oscillation is unstable when restarted. for this reason, time for stabilizing of oscillation (oscillation stabilizing time) is required. the input of the reset pin should be held at the ??level until oscillation stabilizes. when the reset pin is held at the ??level for 16 cycles or more of x in after the oscillation has stabilized, the microcomputer will go to the reset state. after the input level of the reset pin is returned to ?? the reset state is released in approximately 10.5 to 18.5 cycles of the x in input. figure 2.13.1 shows the oscillation stabilizing time at restoration by reset input. at release of the stop mode by reset input, the internal ram retains its contents previous to the reset. however, the previous contents of the cpu register and sfr are not retained. for more details concerning reset, refer to ?.11 reset? fig. 2.13.1 oscillation stabilizing time at restoration by reset input vcc reset x in stop mode oscillation stabilizing time 16 cycles or more of x in operating mode time to hold internal reset state = approximately 10.5 to 18.5 cycles of x in input execute stop instruction (note) note: some cases may occur in which no waveform is input to x in (in low-speed mode).
3886 group user s manual application 2-149 2.13 standby function restoration by interrupt request the occurrence of an interrupt request in the stop mode releases the stop mode. as a result, oscillation is resumed. the interrupts available for restoration are: int 0 int 4 cntr 0 , cntr 1 serial i/o (1, 2) using an external clock timer x, y using an external event count key input (key-on wake-up) bus interface s cl /s da however, when using any of these interrupt requests for restoration from the stop mode, in order to enable the selected interrupt, you must execute the stp instruction after setting the following conditions. [necessary register setting] ? interrupt disable flag i = 0 (interrupt enabled) ? timer 1 interrupt enable bit = 0 (interrupt disabled) ? interrupt request bit of interrupt source to be used for restoration = 0 (no interrupt request issued) ? interrupt enable bit of interrupt source to be used for restoration = 1 (interrupts enabled) for more details concerning interrupts, refer to 2.2 interrupts . oscillation is unstable when restarted. for this reason, time for stabilizing of oscillation (oscillation stabilizing time) is required. for restoration by an interrupt request, waiting time prior to supplying internal clock to the cpu is automatically generated ? 2 by prescaler 12 and timer 1 ? 1 . this waiting time is reserved as the oscillation stabilizing time on the system clock side. the supply of internal clock to the cpu is started at the timer 1 underflow. figure 2.13.2 shows an execution sequence example at restoration by the occurrence of an int 0 interrupt request. ? 1: if the stp instruction is executed when the oscillation stabilizing time set after stp instruction released bit is 0 , ff 16 and 01 16 are automatically set in the prescaler 12 counter/latch and timer 1 counter/latch, respectively. when the oscillation stabilizing time set after stp instruction released bit is 1 , nothing is automatically set to either prescaler 12 or timer 1. for this reason, any suitable value can be set to prescaler 12 and timer 1 for the oscillation stabilizing time. ? 2: immediately after the oscillation is started, the count source is supplied to the prescaler 12 so that a count operation is started.
3886 group user s manual application 2.13 standby function 2-150 fig. 2.13.2 execution sequence example at restoration by occurrence of int 0 interrupt request (3) notes on using stop mode restarting oscillation usually, when the mcu stops the clock oscillation by stp instruction and the stp instruction has been released by an external interrupt source, the fixed values of timer 1 and prescaler 12 (timer 1 = 01 16 , prescaler 12 = ff 16 ) are automatically reloaded in order for the oscillation to stabilize. the user can inhibit the automatic setting by writing 1 to bit 6 of the port control register 2 (address 002f 16 ). however, by setting this bit to 1 , the previous values, set just before the stp instruction was executed, will remain in timer 1 and prescaler 12. therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the stp instruction. reason oscillation will restart when an external interrupt is received. however, internal clock phi is supplied to the cpu only when timer 1 underflows. this ensures time for the clock oscillation using the ceramic resonators to be stabilized. stop mode x in or x cin (system clock) int 0 pin prescaler 12 counter timer 1 counter int 0 interrupt request bit peripheral device cpu operating operating stopped stopped operating operating 512 counts oscillation stabilizing time x in ; h x cin ; in high-impedance state ff 16 01 16 execute stp instruction int 0 interrupt signal input (int 0 interrupt request occurs) oscillation start prescaler 12 count start 512 counts down by prescaler 12 start supplying internal clock to cpu accept int 0 interrupt request note: f(x in )/16 or f(x cin )/16 is input as the prescaler 12 count source. when restoring microcomputer from stop mode by int 0 interrupt (rising edge selected)
3886 group user s manual application 2-151 2.13 standby function 2.13.2 wait mode the wait mode is set by execution of the wit instruction. in the wait mode, oscillation continues, but the internal clock stops at the h level. the cpu stops, but most of the peripheral units continue operating. (1) state in wait mode the continuation of oscillation permits clock supply to the peripheral units except i 2 c-bus interface. table 2.13.2 shows the state in the wait mode. table 2.13.2 state in wait mode item oscillation cpu internal clock i/o ports p0 p8 timer pwm0, pwm1 watchdog timer serial i/o1, serial i/o2 i 2 c-bus interface a-d converter d-a converter comparator bus interface state in wait mode operating. stopped. stopped at h level. retains the state at the wit instruction execution. operating. operating. operating. operating. stopped. however, this operates when the system clock stop selection bit (bit 6 of address 15 16 ) is 1 . operating. retains output voltage. operating. operating. clock restoration after restoration from the stop mode to the normal mode by an interrupt request, the contents of the cpu mode register previous to the stp instruction execution are retained. accordingly, if both main clock and sub clock were oscillating before execution of the stp instruction, the oscillation of both clocks is resumed at restoration. in the above case, when the main clock side is set as a system clock, the oscillation stabilizing time for approximately 8,000 cycles of the x in input is reserved at restoration from the stop mode. at this time, note that the oscillation on the sub clock side may not be stabilized even after the lapse of the oscillation stabilizing time of the main clock side.
3886 group user s manual application 2.13 standby function 2-152 (2) release of wait mode the wait mode is released by reset input or by the occurrence of an interrupt request. note the differences in the restoration process according to reset input or interrupt request, as described below. in the wait mode, oscillation is continued, so an instruction can be executed immediately after the wait mode is released. restoration by reset input the wait mode is released by holding the input level of the reset pin at l in the wait mode. upon release of the wait mode, all ports are in the input state, and supply of the internal clock to the cpu is started. to reset the microcomputer, the reset pin should be held at an l level for 16 cycles or more of x in . the reset state is released in approximately 10.5 cycles to 18.5 cycles of the x in input after the input of the reset pin is returned to the h level. at release of wait mode, the internal ram retains its contents previous to the reset. however, the previous contents of the cpu register and sfr are not retained. figure 2.13.3 shows the reset input time. for more details concerning reset, refer to 2.11 reset . fig. 2.13.3 reset input time vcc reset x in wait mode 16 cycles of x in operating mode time to hold internal reset state = approximately 10.5 to 18.5 cycles of x in input note: some cases may occur in which no waveform is input to x in (in low-speed mode). (note) execute wit instruction
3886 group user s manual application 2-153 2.13 standby function restoration by interrupt request in the wait mode, the occurrence of an interrupt request releases the wait mode and supply of the internal clock to the cpu is started. at the same time, the interrupt request used for restoration is accepted, so the interrupt processing routine is executed. however, when using an interrupt request for restoration from the wait mode, in order to enable the selected interrupt, you must execute the stp instruction after setting the following conditions. [necessary register setting] ? interrupt disable flag i = 0 (interrupt enabled) ? interrupt request bit of interrupt source to be used for restoration = 0 (no interrupt request issued) ? interrupt enable bit of interrupt source to be used for restoration = 1 (interrupts enabled) for more details concerning interrupts, refer to 2.2 interrupts . (3) notes on wait mode clock restoration if the wait mode is released by a reset when x cin is set as the system clock and x in oscillation is stopped during execution of the wit instruction, x cin oscillation stops, x in oscillations starts, and x in is set as the system clock. in the above case, the reset pin should be held at l until the oscillation is stabilized.
3886 group user? manual application 2.14 processor mode 2.14 processor mode this paragraph explains usage examples and others relevant to the processor mode. (support product: m3886 7m8a/e8a) 2.14.1 memory map fig. 2.14.1 memory map of registers relevant to processor mode 2.14.2 relevant registers fig. 2.14.2 structure of cpu mode register 0 0 3 b 1 6 c p u m o d e r e g i s t e r ( c p u m ) cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 cpu mode register (cpum: address 3b 16 ) 00 : single-chip mode 01 : memory expansion mode (note) 10 : microprocessor mode (note) 11 : not available b 0 1 1 2 3 4 5 6 7 name 0 functions at reset r w 0 : 0 page 1 : 1 page 0 1 0 0: oscillating 1: stopped 0 1 0 processor mode bits stack page selection bit port xc switch bit fix this bit to 1 . main clock (x in - x out ) stop bit main clock division ratio selection bits * : the initial value of bit 1 depends on the cnvss level. note: this mode is not available for m3886 9m8a/mca/mfa or the flash memory version. b1 b0 b7 b6 0 0: =f(x in )/2 (high-speed mode) 0 1: =f(x in )/8 (middle-speed mode) 1 0: =f(x cin )/2 (low-speed mode) 1 1: not available 0: i/o port function (oscillation stopped) 1: x cin -x cout oscillation function *
3886 group user s manual application 2-155 2.14 processor mode 2.14.3 processor mode usage examples (1) external memory connection example unusing onw (one wait) function outline : an external memory is accessed, using the microprocessor mode. the ram which meets the following conditions can be used at f(x in ) = 8 mhz: oe access time: t a(oe) 50 ns data set up time at write: t su(d) 65 ns. for example, the m5m5256bp-10, whose address access time is 100 ns, can be used. figure 2.14.3 shows the expansion example of 32-kbytes rom and ram. fig. 2.14.3 expansion example of 32-kbytes rom and ram 3 8 8 6 g r o u p c n v s s o n w a d 1 5 8 p 4 8 p 5 8 p 6 a d 1 4 t o a d 0 d b 0 t o d b 7 r d wr m5m27c256ak-10 m 5 m 5 2 5 6 b p - 1 0 c e a 0 to a 14 d 0 t o d 7 o e a 0 to a 14 dq 1 to dq 8 oe w 8 mhz v cc = 5.0 v 10 % external ram area (m5m5256bp) sfr area internal ram area external ram area (m5m5256bp) external rom area (m5m27c256ak) 0000 16 8 0 0 0 1 6 0440 16 0 0 4 0 1 6 0 0 0 8 1 6 ffff 16 memory map 7 4 f 0 4 s 15 8 2 p3 0 , p3 1 eprom sram 8 p7 8 p 8
3886 group user s manual application 2.14 processor mode figures 2.14.4 to 2.14.6 show the basic timing at 8 mhz (no wait) operating. fig. 2.14.4 read cycle (oe access, sram) fig. 2.14.5 read cycle (oe access, eprom) 50 ns ( max. ) 6 5 n s ( m i n . ) a 0 t o a 7 ( p o r t p 0 ) a 8 t o a 1 4 ( p o r t p 1 ) data dq 1 to dq 8 (port p2) s ( a d 1 5 ) w ( 3 8 8 6 g r o u p s w r ) h l e v e l 125 ns 10 ns ( m i n. ) 1 2 5 n s 4 0 n s ( m i n . ) oe (3886 group s rd) td(al rd) t w l ( r d ) ta(oe) t s u ( d b r d ) td(al rd) : rd delay time after address output of 3886 group t wl (rd) : rd pulse width of 3886 group ta(oe) : output enable access time of m5m5256bp tsu(db rd) : data bus set up time before rd of 3886 group l o w - o r d e r a d d r e s s h i g h - o r d e r a d d r e s s 5 0 n s ( m a x . ) 65 ns ( m i n. ) a 0 t o a 7 ( p o r t p 0 ) a 8 to a 14 (port p1) d a t a d 0 t o d 7 ( p o r t p 2 ) c e 5 . 8 n s ( m a x . ) t p h l 1 2 5 n s 1 0 n s ( m i n . ) 125 ns 40 ns ( m i n. ) o e ( 3 8 8 6 g r o u p s r d ) t d ( a l r d ) t wl (rd) ta(oe) t s u ( d b r d ) t phl : output delay time of 74f04 td(al rd) : rd delay time after address output of 3886 group t wl (rd) : rd pulse width of 3886 group ta(oe) : output enable access time of m5m27c256ak tsu(db rd) : data bus set up time before rd of 3886 group low-order address high-order address
3886 group user s manual application 2-157 2.14 processor mode fig. 2.14.6 write cycle (w control, sram) t d ( a l w r ): w r d e l a y t i m e a f t e r a d d r e s s o u t p u t o f 3 8 8 6 g r o u p t w l ( w r ): w r p u l s e w i d t h o f 3 8 8 6 g r o u p t d ( w r d b ): d a t a b u s d e l a y t i m e a f t e r w r o f 3 8 8 6 g r o u p t s u ( d ): d a t a s e t u p t i m e o f m 5 m 5 2 5 6 b p 65 ns ( max. ) 3 5 n s ( m i n . ) data dq 1 to dq 8 (port p2) s ( a d 1 5 ) oe (3886 group s rd) h l eve l 125 ns 10 ns ( m i n. ) 1 2 5 n s 4 0 n s ( m i n . ) w ( 3 8 8 6 g r o u p s w r ) t d ( a l w r ) t w l ( w r ) td(wr db) tsu(d) a 0 t o a 7 ( p o r t p 0 ) a 8 to a 14 (port p1) low-order address h i g h - o r d e r a d d r e s s
3886 group user s manual application 2.14 processor mode (2) external memory connection example using onw (one wait) function outline : when the access time of an external memory is slow, the onw function is used. when l level is input to the p3 2 /onw pin in the state that the cpu reads or writes, a read or write cycle is extended by one cycle of . the rd or wr signal retains l level during the extended time. the onw function is valid for read or write to addresses 0000 16 to 0007 16 and 0440 16 to ffff 16 . figure 2.14.7 shows the usage example using the onw function. fig. 2.14.7 usage example of onw function 3 8 8 6 g r o u p c n v s s a d 1 5 8 p5 8 p6 onw a d 1 4 t o a d 0 d b 0 t o d b 7 rd w r m5m27c256ak-10 m 5 m 5 2 5 6 b p - 1 0 c e a 0 t o a 1 4 d 0 t o d 7 o e a 0 to a 14 dq 1 to dq 8 oe w 8 m h zv cc = 5.0 v 10 % e x t e r n a l r a m a r e a ( m 5 m 5 2 5 6 b p ) sfr area internal ram area e x t e r n a l r o m a r e a ( m 5 m 2 7 c 2 5 6 a k ) 0000 16 8000 16 0440 16 0040 16 0008 16 ffff 16 m e m o r y m a p 7 4 f 0 4 s 15 8 8 p4 2 p3 0 , p3 1 e p r o msram external ram area (m5m5256bp)
3886 group user s manual application 2-159 2.14 processor mode (3) external memory connection example at f(x in ) = 8 mhz or more outline : when the access time of an external memory is fast, it is possible to use at f(x in ) = 8 mhz or more. the ram which meets the following conditions can be used at f(x in ) = 9 mhz: oe access time: t a(oe) 35 ns data set up time at write: t su(d) 50 ns. for example, the m5m5256bp-70, whose address access time is 70 ns, can be used. figure 2.14.8 shows the expansion example of 32-kbytes rom and ram. fig. 2.14.8 expansion example of 32-kbytes rom and ram at f(x in ) = 8 mhz or more 3 8 8 6 g r o u p c n v s s o n w a d 1 5 8 p4 8p 5 8 p 6 ad 14 to ad 0 d b 0 t o d b 7 r d wr m 5 m 2 7 c 2 5 6 a k - 8 5 m5m5256bp-70 c e a 0 t o a 1 4 d 0 t o d 7 oe a 0 t o a 1 4 dq 1 to dq 8 oe w 9mhz v cc = 5.0 v 10 % external ram area (m5m5256bp) sfr area internal ram area external ram area (m5m5256bp) e x t e r n a l r o m a r e a ( m 5 m 2 7 c 2 5 6 a k ) 0000 16 8000 16 0440 16 0040 16 0008 16 ffff 16 memory map 7 4 f 0 4 s 15 8 2 p3 0 , p3 1 eprom sram 8 p 7 8 p8
3886 group user s manual application 2.14 processor mode figures 2.14.9 to 2.14.11 show the basic timing at 9 mhz (no wait) operating. fig. 2.14.9 read cycle (oe access, sram) fig. 2.14.10 read cycle (oe access, eprom) 35 ns ( max. ) 5 0 n s ( m i n . ) a 0 t o a 7 ( p o r t p 0 ) h i g h - o r d e r a d d r e s s a 8 t o a 1 4 ( p o r t p 1 ) data dq 1 to dq 8 (port p2) s (ad15) w r h l e v e l 1 1 1 n s 1 0 n s ( m i n . ) 111 ns 40ns ( m i n. ) o e ( 3 8 8 6 g r o u p s r d ) t d ( a l r d ) t wl (rd) ta(oe) tsu(db rd) t d ( a l r d ): r d d e l a y t i m e a f t e r a d d r e s s o u t p u t o f 3 8 8 6 g r o u p t w l ( r d ): r d p u l s e w i d t h o f 3 8 8 6 g r o u p t a ( o e ): o u t p u t e n a b l e a c c e s s t i m e o f m 5 m 5 2 5 6 b p t s u ( d b r d ): d a t a b u s s e t u p t i m e b e f o r e r d o f 3 8 8 6 g r o u p l o w - o r d e r a d d r e s s 45 ns ( max. ) 5 0 n s ( m i n . ) a 0 t o a 7 ( p o r t p 0 ) high-order address a 8 t o a 1 4 ( p o r t p 1 ) d a t a d 0 to d 7 (port p2) w r h l e v e l c e 5 . 8 n s ( m a x . ) t p h l 111 ns 10ns ( m i n. ) 1 1 1 n s 4 0 n s ( m i n . ) o e ( 3 8 8 6 g r o u p s r d ) td(al rd) t wl (rd) t a ( o e ) tsu(db rd) t p h l : o u t p u t d e l a y t i m e o f 7 4 f 0 4 t d ( a l r d ): r d d e l a y t i m e a f t e r a d d r e s s o u t p u t o f 3 8 8 6 g r o u p t w l ( r d ): r d p u l s e w i d t h o f 3 8 8 6 g r o u p t a ( o e ): o u t p u t e n a b l e a c c e s s t i m e o f m 5 m 2 7 c 2 5 6 a k t s u ( d b r d ): d a t a b u s s e t u p t i m e b e f o r e r d o f 3 8 8 6 g r o u p low-order address
3886 group user s manual application 2-161 2.14 processor mode fig. 2.14.11 write cycle (w control, sram) 30 ns ( max. ) 30 ns ( m i n. ) h i g h - o r d e r a d d r e s s data d q 1 t o d q 8 ( p o r t p 2 ) s ( a d 1 5 ) o e ( 3 8 8 6 g r o u p s r d ) h l eve l 111 ns 10 ns ( m i n. ) 1 1 1 n s 3 5 n s ( m i n . ) w ( 3 8 8 6 g r o u p s w r ) t d ( a l w r ) t w l ( w r ) td(wr db) tsu(d) a 0 t o a 7 ( p o r t p 0 ) a 8 t o a 1 4 ( p o r t p 1 ) t d ( a l w r ): w r d e l a y t i m e a f t e r a d d r e s s o u t p u t o f 3 8 8 6 g r o u p t w l ( w r ): w r p u l s e w i d t h o f 3 8 8 6 g r o u p t d ( w r d b ): d a t a b u s d e l a y t i m e a f t e r w r o f 3 8 8 6 g r o u p t s u ( d ): d a t a s e t u p t i m e o f m 5 m 5 2 5 6 b p l o w- o r d e r a d d r e s s
3886 group user? manual application 2.15 flash memory fig. 2.15.1 memory map of flash memory version for 3886 group 2.15 flash memory this paragraph explains the registers setting method and the notes relevant to the flash memory version. 2.15.1 overview the functions of the flash memory version are similar to those of the mask rom version except that the flash memory is built-in and some of the sfr area differ from that of the mask rom version (refer to ?.15.2 memory map?. in the flash memory version, the built-in flash memory can be programmed or erased by using the following three modes. ?cpu reprogramming mode ?parallel input/output mode ?serial input/output mode 2.15.2 memory map m3886 9ffahp/gp have 60 kbytes of built-in flash memory. figure 2.15.1 shows the memory map of the flash memory version. s f r a r e a internal ram area (2 kbytes) not used sfr area 0 0 0 0 1 6 0 0 4 0 1 6 0 8 3 f 1 6 0 8 4 0 1 6 0 f f 0 1 6 1 0 0 0 1 6 f f f f 1 6 ram 1 0 0 0 1 6 7fff 16 8 0 0 0 1 6 f f f f 1 6 28 kbytes 3 2 k b y t e s user rom area 0 f f f 1 6 b u i l t - i n f l a s h m e m o r y a r e a ( 6 0 k b y t e s ) n o t u s e d
3886 group user s manual application 2-163 2.15 flash memory fig. 2.15.3 structure of flash memory control register fig. 2.15.2 memory map of registers relevant to flash memory 2.15.3 relevant registers 0 f f e 1 6 f l a s h m e m o r y c o n t r o l r e g i s t e r ( f c o n ) f l a s h c o m m a n d r e g i s t e r ( f c m d ) 0 f f f 1 6 flash memory control register b7 b6 b5 b4 b3 b2 b1 b0 flash memory control register (fcon : address ffe 16 ) b 0 00 1 2 4 name 0 functions at reset r w 0 0 0 0 erase/program busy flag fix this bit to 0 . erase/program area select bits cpu reprogramming mode monitor flag 0 : cpu reprogramming mode is invalid. (normal operation mode) 1 : when applying 0 v to cnv ss /v pp pin, cpu reprogramming mode is invalid. when applying v pp h to cnv ss /v pp pin, cpu reprogramming mode is valid. 0 : erase and program are completed or have not been executed. 1 : erase/program is being executed. 0 : cpu reprogramming mode is invalid 1 : cpu reprogramming mode is valid 5 0 6 7 0 fix this bit to 0 . 0 cpu reprogramming mode select bit (note) nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are 0 . note: bit 0 can be reprogrammed only when 0 v is applied to the cnv ss /v pp pin. 3 b5 b4 0 0: address 1000 16 to ffff 16 (total 60kbytes) 0 1: address 1000 16 to 7fff 16 (total 28kbytes) 1 0: address 8000 16 to ffff 16 (total 32kbytes) 1 1: not available
3886 group user s manual application 2.15 flash memory fig. 2.15.4 structure of flash command register 2.15.4 parallel i/o mode in the parallel i/o mode, program/erase to the built-in flash memory can be performed by a general eprom programmer. set the programming mode of the eprom programmer to m5m28f101 and set the memory area of program/erase from 01000 16 to 0ffff 16 . be especially careful when erasing; if the memory area is not set correctly, the products will be damaged eternally. table 2.15.1 shows the setting of eprom programmers when programming in the parallel i/o mode. table 2.15.1 setting of eprom programmers when parallel programming products m3886 9ffahp m3886 9ffagp programming adapter pca4738hf-80 pca4738gf-80 programming mode m5m28f101 memory area 01000 16 to 0ffff 16 flash command register b7 b6 b5 b4 b3 b2 b1 b0 flash command register (fcmd: address fff 16 ) b 0 0 at reset r w 1 2 3 4 5 6 7 functions writing of software command read command program command program verify command erase command erase verify command reset command 00 16 40 16 c0 16 20 16 + 20 16 a0 16 ff 16 + ff 16 note: the flash command register is a write-only register. 0 0 0 0 0 0 0
3886 group user s manual application 2-165 2.15 flash memory 2.15.5 serial i/o mode table 2.15.2 shows a pin connection example using msp-i/msp-ii ? between the programmer and the microcomputer when programming in the serial i/o mode. ? msp-i/msp-ii provided by suisei electronics system co., ltd. (http://www.suisei.co.jp/index_e.htm) (product available in asia and oceania only) table 2.15.2 connection example to programmer when serial programming msp-i/msp-ii signal name busy vpp ( note 1 ) vdd ( note 3 ) scl sda pgm/oe reset gnd ( note 2 ) target connector line number 1 2 3 4 5 6 7 8 pin name p4 7 /s rdy1 cnv ss ( note 1 ) v cc ( note 3 ) p4 6 /s clk1 p4 4 /rxd p3 7 reset v ss , av ss ( note 2 ) pin number 18 24 71 19 21 55 25 30, 73 3886 group flash memory version notes 1: connect an approximate 0.01 f capacitor between cnv ss /v pp and gnd for noise elimination. 2: when connecting a serial programmer, first connect both gnds to the same gnd level. 3: when the v cc power is already supplied to the target board, do not connect the vdd supply pin of the serial programmer to v cc of the target board.
3886 group user s manual application 2.15 flash memory 2.15.6 cpu reprogramming mode in the cpu reprogramming mode, issuing software commands through the central processing unit (cpu) can reprogram the built-in flash memory. accordingly, the contents of the built-in flash memory can be reprogrammed with the microcomputer itself mounted on board, without using the eprom programmer. store the reprogramming control program to the built-in flash memory in advance. the built-in flash memory cannot be read in the cpu reprogramming mode. accordingly, after transferring the reprogramming control program to the internal ram, execute it on the ram. the following commands can be used in the cpu reprogramming mode: read, program, program verify, erase, erase verify, and reset. for details concerning each command, refer to chapter 1 flash memory mode 3 (cpu reprogramming mode) . (1) cpu reprogramming mode beginning/release procedures operation procedure in the cpu reprogramming mode for the built-in flash memory is described below. as for the control example, refer to 2.15.7 (2) control example in the cpu reprogramming mode. [beginning procedure] ? apply 0 v to the cnv ss /v pp pin for reset release. ? after cpu reprogramming mode control program is transferred to internal ram, jump to this control program on ram. (the following operations are controlled by this control program). ? set 1 to the cpu reprogramming mode select bit (bit 0 of address 0ffe 16 ). ? apply v pp h to the cnv ss /v pp pin. ? wait until cnv ss /v pp pin becomes 12 v. ? read the cpu reprogramming mode monitor flag (bit 2 of address 0ffe 16 ) to confirm that the cpu reprogramming mode is valid. ? flash memory operations are executed by writing software-commands to the flash command register (address 0fff 16 ). note: the following procedures are also necessary. control for data which is input from the external (serial i/o etc.) and to be programmed to the flash memory. initial setting for ports, etc. writing to the watchdog timer [release procedure] ? apply 0 v to the cnv ss /v pp pin. ? wait until cnv ss /v pp pin becomes 0 v. ? set the cpu reprogramming mode select bit (bit 0 of address 0ffe 16 ) to 0 .
3886 group user s manual application 2-167 2.15 flash memory also, execute the following processing before the cpu reprogramming mode is selected so that interrupts will not occur during the cpu reprogramming mode. set the interrupt disable flag (i) to 1 in the cpu reprogramming mode, write to the watchdog timer control register (address 1e 16 ) periodically to prevent the generation of a reset by the underflow of the watchdog timer h. in the program state (programming time: max. 9.5 s), watchdog timer h and l are set to ff 16 , and the count stop. the count is started again after the program state or the erase state is completed. accordingly, the write period of the watchdog timer control register is calculated except for the program time and erase time. when the interrupt request or reset occurs in the cpu reprogramming mode, the microcomputer enters the following states; (1) interrupt this may cause a program runaway because the flash memory that has an interrupt vector area cannot be read. (2) underflow of watchdog timer h, reset this may cause a microcomputer reset; the built-in flash memory control circuit and the flash memory control register are reset. also, note that, when the interrupt or reset occurs during program/erase, error data may still exist after reset release because the reprogramming of the flash memory has not been completed. in this case, setting the proper program code to the flash memory in the parallel i/o mode or serial i/o mode is required. 2.15.7 flash memory mode application examples the control pin processing example on the system board in the serial i/o mode and the control example in the cpu reprogramming mode are described below. (1) control pin connection example on the system board in serial i/o mode as shown in figure 2.15.5, in the serial i/o mode, the built-in flash memory can be reprogrammed with the microcomputer mounted on board. connection examples of control pins (p3 7 , p4 4 , p4 6 , p4 7 , cnv ss and reset pin) in the serial i/o mode are described below. fig. 2.15.5 reprogramming example of built-in flash memory in serial i/o mode m a s t e r r o m r s - 2 3 2 c serial programmer m 3 8 8 6 9 f f
3886 group user s manual application 2.15 flash memory ? when control signals are not affected to user system circuit when the control signals in the serial i/o mode are not used or not affected to the user system circuit, they can be connected as shown in figure 2.15.6. fig. 2.15.6 connection example in serial i/o mode (1) ? when control signals are affected to user system circuit-1 figure 2.15.7 shows an example that the jumper switch cut-off the control signals not to supply to the user system circuit in the serial i/o mode. fig. 2.15.7 connection example in serial i/o mode (2) m 3 8 8 6 9 f f target board reset v p p ( c n v s s ) s d a ( p 4 4 ) s c l k ( p 4 6 ) o e ( p 3 7 ) x in x o u t b u s y ( p 4 7 ) user reset signal (low active) n o t u s e d o r t o u s e r s y s t e m c i r c u i t : w h e n n o t u s e d , s e t t o i n p u t m o d e a n d p u l l u p o r p u l l d o w n , o r s e t t o o u t p u t m o d e a n d o p e n . v s s v c c a v s s * * m 3 8 8 6 9 f f t a r g e t b o a r d r e s e t v p p ( c n v s s ) x i n x o u t u s e r r e s e t s i g n a l ( l o w a c t i v e ) t o u s e r s y s t e m c i r c u i t s d a ( p 4 4 ) s c l k ( p 4 6 ) o e ( p 3 7 ) b u s y ( p 4 7 ) v s s v c c a v s s
3886 group user s manual application 2-169 2.15 flash memory ? when control signals are affected to user system circuit-2 figure 2.15.8 shows an example that the analog switch (74hc4066) cut-off the control signals not to supply to the user system circuit in the serial i/o mode. fig. 2.15.8 connection example in serial i/o mode (3) m 3 8 8 6 9 f f r e s e t v p p ( c n v s s ) s d a ( p 4 4 ) s c l k ( p 4 6 ) o e ( p 3 7 ) x in x o u t b u s y ( p 4 7 ) user reset signal (low active) t a r g e t b o a r d t o u s e r s y s t e m c i r c u i t 7 4 h c 4 0 6 6 v s s v c c a v s s
3886 group user s manual application 2.15 flash memory (2) control example in cpu reprogramming mode in this example, the built-in flash memory is reprogrammed in the cpu reprogramming mode by serial i/o, receiving the reprogramming data (updated data). figure 2.15.9 shows an example of the reprogramming system for the built-in flash memory in the cpu reprogramming mode. fig. 2.15.9 example of reprogramming system for built-in flash memory in cpu reprogramming mode specifications ? cpu reprogramming mode is selected/released by the input signal to pi 2 . ? updated data is received by serial i/o. ? the transfer enable state of serial transmit side is judged by l level input to pi 0 . ? v pp control circuit is turned on/off by the output from pi 1 (refer to figure 2.15.14 and figure 2.15.15). v p p c i r c u i t c o n t r o l p o r t m 3886 9 ff v p p ( c n v s s ) x i n x o u t pi 2 user reset signal v pp * control circuit pi 1 10 mhz clk 1 rxd 1 txd 1 pi 0 p o r t f o r c p u r e p r o g r a m m i n g m o d e s w i t c h ( c p u r e p r o g r a m m i n g m o d e i s s e l e c t e d / r e l e a s e d b y p o r t p i 2 i n p u t s i g n a l ) v c c v s s r e s e t (i = 0 to 8) reprogramming data input control (updated data is received by serial i/o) refer to figure 2.15.14 and figure 2.15.15. * on/off of v pp control circuit is controlled by port pi 1 output. 0v 1 2 v
3886 group user s manual application 2-171 2.15 flash memory fig. 2.15.10 cpu reprogramming control program example (1) * 1 : w a i t i n g b y s o f t w a r e u n t i l v p p i n p u t v o l t a g e i s s t a b i l i z e d a t v p p h i s r e c o m m e n d e d . ( r e f e r t o f i g u r e s 2 . 1 5 . 1 4 a n d 2 . 1 5 . 1 5 v p p v o l t a g e c o n t r o l t i m i n g a . ) * 2 : t h e w a i t i n g t i m e d e p e n d s o n v p p c o n t r o l c i r c u i t ( r e f e r t o f i g u r e s 2 . 1 5 . 1 4 a n d 2 . 1 5 . 1 5 v p p v o l t a g e c o n t r o l t i m i n g c . ) c p u r e p r o g r a m m i n g m o d e s e l e c t b i t = 1 p ort pi 1 = 1 i n t e r r u p t d i s a b l e p r o c e s s i n g n o y e s wa i t 5 m s c p u r e p r o g r a m m i n g m o d e m o n i t o r f l a g = 1 ? n o y e s *2 c p u r e p r o g r a m m i n g c o n t r o l p r o g r a m e x a m p l e s e r i a l i / o i n i t i a l i z a t i o n s e t n o t e : i n t h i s e x a m p l e , t h e f o l l o w i n g p r o g r a m i s t r a n s f e r r e d t o a n d e x e c u t e d o n t h e i n t e r n a l r a m . a p p l y v p p v o l t a g e = v p p h w a i t i n g f o r s t a b i l i z a t i o n * 1 c p u r e p r o g r a m m i n g m o d e m o n i t o r f l a g = 1 ? i n t h i s p r o g r a m e x a m p l e , t h e f l a s h m e m o r y i s r e p r o g r a m m e d b y r e c e i v i n g e a c h 1 b y t e o f d a t a f r o m s e r i a l i / o . 1 2 v a p p l i e d c i r c u i t t o v p p o n ? t r a n s i t i o n t o c p u r e p r o g r a m m i n g m o d e i n i t i a l i z e w a t c h d o g t i m e r ( w r i t e t o w a t c h d o g t i m e r c o n t r o l r e g i s t e r ) t o p r e v e n t g e n e r a t i o n o f w a t c h d o g t i m e r i n t e r r u p t d u r i n g t h i s p r o c e s s i n g . confirmation that cpu reprogramming mode is valid. c o n t i n u e d t o c p u r e p r o g r a m m i n g c o n t r o l p r o g r a m e x a m p l e ( 2 ) o n t h e n e x t p a g e . ? preparing for transition to cpu reprogramming mode disable the interrupt of built-in peripheral functions in this processing. also, initialize watchdog timer (write to watchdog timer control register) to prevent generation of watchdog timer interrupt.
3886 group user s manual application 2.15 flash memory fig. 2.15.11 cpu reprogramming control program example (2) c o n t i n u e d t o c p u r e p r o g r a m m i n g c o n t r o l p r o g r a m e x a m p l e ( 4 ) o n t h e p a g e a f t e r n e x t s e t er a s e v e r i f y s t a r t a d d r e s s n o y e s no yes y e s pass fail n o a l l a d d r e s s e s = 0 0 1 6 ? p r o g r a m / p r o g r a m v e r i f y p r o c e s s i n g a l l b y t e s = 0 0 1 6 i n i t i a l i z a t i o n o f s o f t w a r e c o u n t e r ( r e t r y c o u n t e r ) f o r e r a s u r e r e t r y c o u n t e r = 0 r e t r y c o u n t e r + 1 i s s u e e r a s e c o m m a n d wait 1 s *1 e r a s e / p r o g r a m b u s y f l a g = 0 ? issue erase verify command wait 6 s *2 e r a s e v e r i f y d a t a c h e c k e r a s e v e r i f y l a s t a d d r e s s erase verify address +1 to a (next page) a0 16 is written to flash command register (address 0fff 16 ) f r o m b ( n e x t p a g e ) 20 16 is written twice continuously to flash command register (address 0fff 16 ) *1: the wait processing time shown in the flow chart is required regardless of the external clock input frequency. *2: the waiting time depends on v pp control circuit (refer to figure 2.15.14 and figure 2.15.15 v pp voltage control timing c.) c o n t i n u e d fr o m c p u r e p r o g r a m m i n g c o n t r o l p r o g r a m e x a m p l e ( 1 ) o n p r e v i o u s p a g e . r e f e r t o ? p r o g r a m / p r o g r a m v e r i f y f o r p r o g r a m / p r o g r a m v e r i f y f l o w c h a r t . ? erasure of reprogramming area initialize watchdog timer (write to watchdog timer control register) to prevent generation of watchdog timer interrupt during this processing.
3886 group user s manual application 2-173 2.15 flash memory fig. 2.15.12 cpu reprogramming control program example (3) * 1 : w a i t i n g b y s o f t w a r e u n t i l v p p i n p u t v o l t a g e i s s t a b i l i z e d a t v p p l i s r e c o m m e n d e d . ( r e f e r t o f i g u r e 2 . 1 5 . 1 4 a n d f i g u r e 2 . 1 5 . 1 5 v p p v o l t a g e c o n t r o l t i m i n g b . ) * 2 : t h e w a i t t i m e d e p e n d s o n v p p c o n t r o l c i r c u i t ( r e f e r t o f i g u r e 2 . 1 5 . 1 4 a n d f i g u r e 2 . 1 5 . 1 5 v p p v o l t a g e c o n t r o l t i m i n g c . ) c p u r e p r o g r a m m i n g m o d e s e l e c t b i t = 0 cpu reprogramm i ng error no y e s n o r e t r y c o u n t e r = 1 0 0 0 ? y e s n o y e s w a i t 5 ms * 2 c o n t i n u e d t o c p u r e p r o g r a m m i n g c o n t r o l p r o g r a m e x a m p l e ( 2 ) o n p r e v i o u s p a g e continued from cpu reprogramming control program example (2) on previous page p o r t p i 1 = 0 apply v pp voltage = v pp l waiting for stabilizing *1 c p u r e p r o g r a m m i n g m o d e m o n i t o r f l a g = 0 ? cpu reprogramming mode select bit = 0 co n t i n u e d f r o m ? ? cpu reprogramming mode release initialize watchdog timer (write to watchdog timer control register) to prevent generation of watchdog timer interrupt during this processing. b a
3886 group user s manual application 2.15 flash memory fig. 2.15.13 cpu reprogramming control program example (4) no y e s issue program command reprogramming data is written to program address n o y e s pass fail n o y e s 12 v applied circuit to v pp off ? c p u r e p r o g r a m m i n g m o d e r e l e a s e i n i t i a l i z e w a t c h d o g t i m e r ( w r i t e t o w a t c h d o g t i m e r c o n t r o l r e g i s t e r ) t o p r e v e n t g e n e r a t i o n o f w a t c h d o g t i m e r i n t e r r u p t d u r i n g t h i s p r o c e s s i n g . n o retry counter + 1 no yes n o y e s ? p r o g r a m / p r o g r a m v e r i f y i n i t i a l i z e w a t c h d o g t i m e r ( w r i t e t o w a t c h d o g t i m e r c o n t r o l r e g i s t e r ) t o p r e v e n t g e n e r a t i o n o f w a t c h d o g t i m e r i n t e r r u p t d u r i n g t h i s p r o c e s s i n g . yes end n o y e s program address + 1 s e t p r o g r a m s t a r t a d d r e s s c o n t i n u e d f r o m c p u r e p r o g r a m m i n g c o n t r o l p r o g r a m e x a m p l e ( 2 ) o n p a g e b e f o r e p r e v i o u s i n i t i a l i z a t i o n o f s o f t w a r e c o u n t e r ( r e t r y c o u n t e r ) f o r r e p r o g r a m m i n g r e t r y c o u n t = 0 reprogramming data receive from serial i/o wa i t 1 s * 1 e rase/program busy flag = 0 ? i ssue program ver if y comman d w a i t 6 s * 1 p r o g r a m v e r i f y d a t a c h e c k p r o g r a m l a s t a d d r e s s p o r t p i 1 = 0 apply v pp voltage = v pp l waiting for stabilizing *2 cpu reprogramming mode monitor flag = 0 ? w a i t 5 m s * 3 cpu reprogramming mode select bit = 0 cpu reprogramming mode select bit = 0 w a i t i ng f or re l ease o f cpu reprogramming mode c p u r e p r o g r a m m i n g m o d e s e l e c t b i t = 0 c p u r e p r o g r a m m i n g e r r o r c p u r e p r o g r a m m i n g m o d e s e l e c t b i t = 0 cpu reprogramming mode monitor flag = 0 ? wait 5 ms *3 port pi 1 = 0 apply v pp voltage = v pp l waiting for stabilizing *2 retry counter = 25? 4 0 1 6 i s w r i t t e n t o f l a s h c o m m a n d r e g i s t e r ( a d d r e s s 0 f f f 1 6 ) c 0 1 6 i s w r i t t e n t o f l a s h c o m m a n d r e g i s t e r ( a d d r e s s 0 f f f 1 6 ) waiting for program completed *1: the wait processing time shown in the flow chart is required regardless of the external clock input frequency. *2: waiting by software until v pp input voltage is stabilized at v pp l is recommended. (refer to figure 2.15.14 and figure 2.15.15 v pp voltage control timing b.) *3: the waiting time depends on v pp control circuit (refer to figure 2.15.14 and figure 2.15.15 v pp voltage control timing c.)
3886 group user s manual application 2-175 2.15 flash memory fig. 2.15.14 v pp control circuit example (1) fig. 2.15.15 v pp control circuit example (2) p i 1 = h pi 1 = l v pp = 12 v v pp = 0 v transition to cpu reprogramming mode enable cannot be allowed until v pp = v pp h. a b 47 k ? 10 k ? rt1n144c 2 2 0 ? 0 . 3 3 f 1 0 0 0 p f 30 k ? 5 k ? 2.7 k ? at off signal = 3 v on/off signal 4.3 k ? 4 7 f 2 s a 1 3 6 4 v i n = 1 2 v mc2848 v p p p i 1 ( v p p c i r c u i t c o n t r o l p o r t ) s y s t e m p o w e r s o u r c e m 5 2 3 7 l 1 k ? c c w h e n 1 2 v v o l t a g e i s s u p p l i e d t o t a r g e t s y s t e m at pi 1 = l output, v pp = 11.8 v at pi 1 = h output, v pp = 0 v input on/off signal so that this point is 1.5 v or more at off state of v pp output. v p p v o l t a g e c o n t r o l t i m i n g t r a n s i t i o n t o c p u r e p r o g r a m m i n g m o d e d i s a b l e c a n n o t b e a l l o w e d u n t i l v p p = v p p l. ? ? ? pi 1 = h pi 1 = l v p p = 1 2 v v p p = 0 v v p p v o l t a g e c o n t r o l t i m i n g a b m 6 2 2 1 2 f p 100 pf 2 2 k ? 1 0 0 f rt1p137p v i n = 5 v 1 k ? 4 7 k ? 1 0 k ? 3 3 k ? 3 . 9 k ? 1 0 0 f 1 k ? v cc c osc c o u t e o u t g n d dtc f b in 1 0 0 ? 0 . 1 f 0 . 1 f 22 k ? ? 5 1 0 0 h r t 1 n 1 4 4 c v p p 1 0 k ? 4 7 k ? 1 0 k ? r t 1 n 1 4 4 c 1 k ? 0 . 1 f 2sd1972 4 7 k ? 1 k ? 2sc3580 c c ( v p p c i r c u i t c o n t r o l p o r t ) p i o n / o f f s i g n a l s c h o t t k y d i o d e a t p i 1 = l o u t p u t , v p p = 1 2 v a t p i 1 = h o u t p u t , v p p = 0 v k e e p v f a s s m a l l a s p o s s i b l e . s y s t e m p o w e r s o u r c e ? ? ? ?? ? ? ? t r a n s i t i o n t o c p u r e p r o g r a m m i n g m o d e e n a b l e c a n n o t b e a l l o w e d u n t i l v p p = v p p h. t r a n s i t i o n t o c p u r e p r o g r a m m i n g m o d e d i s a b l e c a n n o t b e a l l o w e d u n t i l v p p = v p p l . w h e n o n l y 5 v v o l t a g e i s s u p p l i e d t o t a r g e t s y s t e m
3886 group user s manual application 2.15 flash memory 2.15.8 notes on cpu reprogramming mode (1) transfer the cpu reprogramming mode control program to the internal ram before selecting the cpu reprogramming mode, and then, execute it on the internal ram. additionally, when the subroutine or stack operation instruction is used in the control program, make sure the control program is not destroyed by the stack operation. (2) make sure each instruction description (specified address etc.) is correct, because the cpu reprogramming mode control program is transferred to the internal ram and executed on the internal ram. (3) in order to avoid generation of a watchdog timer reset, write to the watchdog timer control register periodically during the cpu reprogramming mode control program (refer to 2.7 watchdog timer ). (4) notes on flash memory version the cnv ss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it works as a program power source pin (v pp pin), as well. to improve the noise margin, connect the cnv ss pin to v ss through 1 to 10 k ? resistor. when the cnv ss pin of the mask rom version is connected to vss through this resistor, the function of mask rom version works well in the same manner as flash memory version.
3886 group user? manual appendix 3.1 electrical characteristics 3-2 3.1 electrical characteristics 3.1.1 absolute maximum ratings table 3.1.1 absolute maximum ratings power source voltage s (note 1) power source voltage s (note 2) input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p8 0 ?8 7 , v ref input voltage p7 0 ?7 7 input voltage reset, x in input voltage cnv ss (note 3) input voltage cnv ss (note 4) input voltage cnv ss (note 5) output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p8 0 ?8 7 , x out output voltage p7 0 ?7 7 power dissipation operating temperature storage temperature v cc v cc v i v i v i v i v i v i v o v o p d t opr t stg symbol parameter conditions ratings ?.3 to 7.0 ?.3 to 6.5 ?.3 to v cc +0.3 ?.3 to 5.8 ?.3 to v cc +0.3 ?.3 to 7 ?.3 to v cc +0.3 ?.3 to 13 ?.3 to v cc +0.3 ?.3 to 5.8 500 ?0 to 85 ?0 to 125 v v v v v v v v v v mw ? ? unit t a = 25 ? all voltages are based on v ss . output transistors are cut off. notes 1: m3886 7m8a, m3886 7e8a 2: m3886 9m8a, m3886 9mca, m3886 9mfa, m3886 9ffa 3: m3886 7m8a 4: m3886 9m8a, m3886 9mca, m3886 9mfa 5: m3886 7e8a, m3886 9ffa
3886 group user? manual appendix 3-3 3.1 electrical characteristics table 3.1.2 recommended operating conditions (1) (v cc = 2.7 to 5.5 v, v cc = 4.0 to 5.5 v for flash memory version, t a = ?0 to 85 ?, unless otherwise noted) 3.1.2 recommended operating conditions 5.5 5.5 5.5 v cc v cc v cc v cc 5.5 5.5 5.5 v cc 5.5 v cc 5.5 v cc 0.2v cc 0.3v cc 0.6 0.2v cc 0.8 0.2v cc 0.16 v cc power source voltage (f(x in ) 4.1 mhz) power source voltage (f(x in ) = 10 mhz) power source voltage (flash memory version) power source voltage analog reference voltage (when a-d converter is used) analog reference voltage (when d-a converter is used) analog power source voltage a-d converter input voltage an 0 ?n 7 ??input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 , p4 1 , p4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p8 0 ?8 7 ??input voltage p7 6 , p7 7 ??input voltage (when i 2 c-bus input level is selected) s da , s cl ??input voltage (when smbus input level is selected) s da , s cl ??input voltage (when cmos input level is selected) p4 2 ?4 6 , dq 0 ?q 7 , w, r, s 0 , s 1 , a 0 ??input voltage (when cmos input level is selected) p7 0 ?7 5 ??input voltage (when ttl input level is selected) p4 2 ?4 6 , dq 0 ?q 7 , w, r, s 0 , s 1 , a 0 (note) ??input voltage (when ttl input level is selected) p7 0 ?7 5 (note) ??input voltage reset, x in , x cin , cnv ss ??input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7, p8 0 ?8 7 ??input voltage (when i 2 c-bus input level is selected) s da , s cl ??input voltage (when smbus input level is selected) s da , s cl ??input voltage (when cmos input level is selected) p4 2 ?4 6 , p7 0 ?7 5 , dq 0 ?q 7 , w, r, s 0 , s 1 , a 0 ??input voltage (when ttl input level is selected) p4 2 ?4 6 , p7 0 ?7 5 , dq 0 ?q 7 , w, r, s 0 , s 1 , a 0 (note) ??input voltage reset, cnv ss ??input voltage x in , x cin v cc v cc v ss v ref av ss v ia v ih v ih v ih v ih v ih v ih v ih v ih v ih v il v il v il v il v il v il v il symbol parameter limits min. v v v v v v v v v v v v v v v v v v v v v v unit 2.7 4.0 4.0 2.0 2.7 av ss 0.8v cc 0.8v cc 0.7v cc 1.4 0.8v cc 0.8v cc 2.0 2.0 0.8v cc 0 0 0 0 0 0 0 5.0 5.0 5.0 0 0 typ. max. note : when v cc is 4.0 to 5.5 v.
3886 group user? manual appendix 3.1 electrical characteristics 3-4 table 3.1.3 recommended operating conditions (2) (v cc = 2.7 to 5.5 v, v cc = 4.0 to 5.5 v for flash memory version, ta = ?0 to 85 ?, unless otherwise noted) ?0 ?0 80 80 40 80 ?0 ?0 40 40 40 40 ??total peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p8 0 ?8 7 (note) ??total peak output current p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 (note) ??total peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 3 , p3 0 ?3 7 , p8 0 ?8 7 (note) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma ma ma unit typ. max. in single-chip mode note : the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. ??total peak output current p2 4 ?2 7 (note) ??total peak output current p4 0 ?4 7 ,p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 (note) ??total average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p8 0 ?8 7 (note) ??total average output current p4 0 ?4 7 ,p5 0 ?5 7 , p6 0 ?6 7 (note) ??total average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 3 , p3 0 ?3 7 , p8 0 ?8 7 (note) ??total average output current p2 4 ?2 7 (note) ??total average output current p4 0 ?4 7 ,p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 (note) in memory expansion mode in microprocessor mode in single-chip mode in memory expansion mode in microprocessor mode table 3.1.4 recommended operating conditions (3) (v cc = 2.7 to 5.5 v, v cc = 4.0 to 5.5 v for flash memory version, t a = ?0 to 85 ?, unless otherwise noted) ?0 10 20 10 ? 5 15 5 10 4.5 v cc ? 10 10 4.5 v cc ? 50 ??peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p8 0 ?8 7 (note 1) ??peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 3 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 (note 1) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) symbol parameter limits min. ma ma ma ma ma ma ma ma mhz mhz mhz mhz mhz khz unit typ. max. in single-chip mode notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) are average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50%. 4: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. 5: when using the timer x/y, timer 1/2, serial i/o1, serial i/o2, a-d converter, comparator, and pwm, set the main clock input os cillation frequency to the max. 4.5v cc ? (mhz). in single-chip mode in memory expansion mode in microprocessor mode in memory expansion mode in microprocessor mode 32.768 f(x cin ) ??peak output current p2 4 ?2 7 (note 1) ??average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p8 0 ?8 7 (note 2) ??average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 3 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 (note 2) ??peak output current p2 4 ?2 7 (note 2) main clock input oscillation frequency (note 3) sub-clock input oscillation frequency (notes 3, 4) high-speed mode 4.0 v v cc 5.5 v high-speed mode 2.7 v v cc 4.0 v middle-speed mode 4.0 v v cc 5.5 v middle-speed mode 2.7 v v cc 4.0 v (note 5) middle-speed mode 2.7 v v cc 4.0 v (note 5)
3886 group user? manual appendix 3-5 3.1 electrical characteristics table 3.1.5 electrical characteristics (1) (v cc = 2.7 to 5.5 v, v cc = 4.0 to 5.5 v for flash memory version, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) 3.1.3 electrical characteristics ??output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 p6 0 ?6 7 , p8 0 ?8 7 (note) ??output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 hysteresis cntr 0 , cntr 1 , int 0 , int 1 int 20 ?nt 40 , int 21 ?nt 41 p3 0 ?3 7 hysteresis rxd, s clk1 , s in2 , s clk2 hysteresis reset ??input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 ??input current reset, cnv ss ??input current x in ??input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 ??input current reset,cnv ss ??input current x in ??input current p3 0 ?3 7 (at pull-up) ram hold voltage limits v v v v v v v a a a a a a a a v parameter min. typ. max. symbol unit note: p0 0 ?0 3 are measured when the p0 0 ?0 3 output structure selection bit of the port control register 1 (bit 0 of address 002e 16 ) is ?? p0 4 ?0 7 are measured when the p0 4 ?0 7 output structure selection bit of the port control register 1 (bit 1 of address 002e 16 ) is ?? p1 0 ?1 3 are measured when the p1 0 ?1 3 output structure selection bit of the port control register 1 (bit 2 of address 002e 16 ) is ?? p1 4 ?1 7 are measured when the p1 4 ?1 7 output structure selection bit of the port control register 1 (bit 3 of address 002e 16 ) is ?? p4 2 , p4 3 , p4 4 , and p4 6 are measured when the p4 output structure selection bit of the port control register 2 (bit 2 of address 002f 16 ) is ?? p4 5 is measured when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is ?? i oh = ?0 ma v cc = 4.0 to 5.5 v i oh = ?.0 ma v cc = 2.7 to 5.5 v i ol = 10 ma v cc = 4.0 to 5.5 v i ol = 1.6 ma v cc = 2.7 to 5.5 v v i = v cc (pin floating. pull-up transistors ?ff? v i = v cc v i = v cc v i = v ss (pin floating. pull-up transistors ?ff? v i = v ss v i = v ss v i = v ss v cc = 4.0 to 5.5 v v i = v ss v cc = 2.7 to 5.5 v when clock stopped v cc ?.0 v cc ?.0 ?0 ?0 2.0 test conditions 0.4 0.5 0.5 4 ? ?0 2.0 0.4 5.0 5.0 ?.0 ?.0 ?20 5.5 v oh v ol v t+ ? t v t+ ? t v t+ ? t i ih i ih i ih i il i il i il i il v ram
3886 group user? manual appendix 3.1 electrical characteristics 3-6 table 3.1.6 electrical characteristics (2) (v cc = 2.7 to 5.5 v, v cc = 4.0 to 5.5 v for flash memory version, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) power source current limits parameter min. typ. max. symbol unit high-speed mode f(x in ) = 10 mhz f(x cin ) = 32.768 khz output transistors ?ff high-speed mode f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors ?ff high-speed mode f(x in ) = 10 mhz (in wit state) f(x cin ) = 32.768 khz output transistors ?ff low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz output transistors ?ff low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors ?ff low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz output transistors ?ff low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors ?ff middle-speed mode f(x in ) = 10 mhz f(x cin ) = stopped output transistors ?ff middle-speed mode f(x in ) = 10 mhz (in wit state) f(x cin ) = stopped output transistors ?ff increment when a-d conversion is executed f(x in ) = 10 mhz all oscillation stopped (in stp state) output transistors ?ff test conditions 15 13 200 40 55 20.0 7.0 1.0 10 i cc ta = 25 ? ta = 85 ? 8.0 6.8 1.6 60 20 20 8.0 4.0 1.5 800 0.1 ma ma ma a a a a ma ma a a a
3886 group user? manual appendix 3-7 3.1 electrical characteristics 3.1.4 a-d converter characteristics bit lsb 2tc(x in ) k ? a a a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a-d port input current min. 12 50 typ. 35 150 max. 10 ? 61 100 200 5 5.0 v cc = v ref = 5.0 v v ref = 5.0 v v ref = 5.0 v table 3.1.7 a-d converter characteristics (1) (v cc = 2.7 to 5.5 v, v cc = 4.0 to 5.5 v for flash memory version, v ref = 2.0 v to v cc , v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) 10-bit a-d mode (when conversion mode selection bit (bit 7 of address 0038 16 ) is ?? unit limits parameter t conv r ladder i vref i i(ad) test conditions at a-d converter operated at a-d converter stopped note 1: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being ?0 16 ? table 3.1.10 comparator characteristics (v cc = 2.7 to 5.5 v, v cc = 4.0 to 5.5 v for flash memory version, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) table 3.1.8 a-d converter characteristics (2) (v cc = 2.7 to 5.5 v, v cc = 4.0 to 5.5 v for flash memory version, v ref = 2.0 v to v cc , v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) 8-bit a-d mode (when conversion mode selection bit (bit 7 of address 0038 16 ) is ?? table 3.1.9 d-a converter characteristics (v cc = 2.7 to 5.5 v, v cc = 4.0 to 5.5 v for flash memory version, v ref = 2.7 v to v cc , v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) symbol bit lsb 2tc(x in ) k ? a a a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a-d port input current min. 12 50 typ. 35 150 max. 8 ? 50 100 200 5 5.0 v cc = v ref = 5.0 v v ref = 5.0 v v ref = 5.0 v unit limits parameter t conv r ladder i vref i i(ad) test conditions at a-d converter operated at a-d converter stopped symbol bits % % s k ? ma resolution absolute accuracy setting time output resistor reference power source input current (note 1) min. 1 typ. 2.5 max. 8 1.0 2.5 3 4 3.2 unit limits parameter tsu ro i vref test conditions v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v symbol lsb s s s v a k ? v v absolute accuracy conversion time analog input voltage analog input current ladder resistor internal reference voltage external reference input voltage min. 0 20 v cc /32 typ. 40 29v cc /32 max. 1/2 2.8 3.5 7 v cc 5.0 50 v cc unit limits parameter t conv v ia i ia r ladder cmp ref test conditions symbol 1lsb = v cc /16 at 10 mhz operating at 8 mhz operating at 4 mhz operating 3.1.5 d-a converter characteristics 3.1.6 comparator characteristics
3886 group user? manual appendix 3.1 electrical characteristics 3-8 3.1.7 timing requirements table 3.1.11 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) reset input ??pulse width main clock input cycle time main clock input ??pulse width main clock input ??pulse width sub-clock input cycle time sub-clock input ??pulse width sub-clock input ??pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input ??pulse width cntr 0 , cntr 1 input ??pulse width t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) limits x in cycles ns ns ns s s s ns ns ns ns ns parameter min. 16 100 40 40 20 5 5 200 80 80 80 80 typ. max. symbol unit note : when bit 6 of address 001a 16 is ??(clock synchronous). divide this value by four when bit 6 of address 001a 16 is ??(uart). t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x d-s clk1 ) t h (s clk1 -r x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) serial i/o1 clock input cycle time (note) serial i/o1 clock input ??pulse width (note) serial i/o1 clock input ??pulse width (note) serial i/o1 input setup time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input ??pulse width serial i/o2 clock input ??pulse width serial i/o2 input setup time serial i/o2 input hold time int 0 , int 1, int 20, int 30, int 40 , int 21, int 31, int 41 input ??pulse width int 0 , int 1, int 20, int 30, int 40 , int 21, int 31, int 41 input ??pulse width 800 370 370 220 100 1000 400 400 200 200 ns ns ns ns ns ns ns ns ns ns
3886 group user? manual appendix 3-9 3.1 electrical characteristics table 3.1.12 timing requirements (2) (v cc = 2.7 to 4.0 v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) reset input ??pulse width main clock input cycle time main clock input ??pulse width main clock input ??pulse width sub-clock input cycle time sub-clock input ??pulse width sub-clock input ??pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input ??pulse width cntr 0 , cntr 1 input ??pulse width t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) limits x in cycles ns ns ns s s s ns ns ns ns ns parameter min. 16 1000/(4.5v cc ?) 400/(4.5v cc ?) 400/(4.5v cc ?) 20 5 5 500 230 230 230 230 typ. max. symbol unit note : when bit 6 of address 001a 16 is ??(clock synchronous). divide this value by four when bit 6 of address 001a 16 is ??(uart). t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x d-s clk1 ) t h (s clk1 -r x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) int 0 , int 1, int 20, int 30, int 40 , int 21, int 31, int 41 input ??pulse width int 0 , int 1, int 20, int 30, int 40 , int 21, int 31, int 41 input ??pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ??pulse width (note) serial i/o1 clock input ??pulse width (note) serial i/o1 input setup time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input ??pulse width serial i/o2 clock input ??pulse width serial i/o2 input setup time serial i/o2 input hold time 2000 950 950 400 200 2000 950 950 400 300 ns ns ns ns ns ns ns ns ns ns
3886 group user? manual appendix 3.1 electrical characteristics 3-10 table 3.1.14 timing requirements for system bus interface (2) (v cc = 2.7 to 4.0 v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) table 3.1.13 timing requirements for system bus interface (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) s 0 , s 1 setup time s 0 , s 1 setup time s 0 , s 1 hold time s 0 , s 1 hold time a0 setup time a0 setup time a0 hold time a0 hold time t su (s-r) t su (s-w) t h (r-s) t h (w-s) t su (a-r) t su (a-w) t h (r-a) t h (w-a) limits ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 0 0 0 0 10 10 0 0 120 120 50 0 typ. max. symbol unit s 0 , s 1 setup time s 0 , s 1 setup time s 0 , s 1 hold time s 0 , s 1 hold time a0 setup time a0 setup time a0 hold time a0 hold time t su (s-r) t su (s-w) t h (r-s) t h (w-s) t su (a-r) t su (a-w) t h (r-a) t h (w-a) limits ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 0 0 0 0 30 30 0 0 250 250 130 0 typ. max. symbol unit read pulse width write pulse width before write data input setup time after write data input hold time t w (r) t w (w) t su (d-w) t h (w-d) read pulse width write pulse width before write data input setup time after write data input hold time t w (r) t w (w) t su (d-w) t h (w-d) 3.1.8 timing requirements for system bus interface
3886 group user? manual appendix 3-11 3.1 electrical characteristics 3.1.9 switching characteristics table 3.1.15 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 -t x d) t v (s clk1 -t x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 t c (s clk2 )/2?60 t c (s clk2 )/2?60 0 typ. 10 10 max. 140 30 30 200 30 30 30 symbol unit notes 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is ?? 2: the x out pin is excluded. test conditions fig. 3.1.1 fig. 3.1.2 fig. 3.1.1 table 3.1.16 switching characteristics (2) (v cc = 2.7 to 4.0 v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 -t x d) t v (s clk1 -t x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 t c (s clk2 )/2?40 t c (s clk2 )/2?40 0 typ. 20 20 max. 350 50 50 400 50 50 50 symbol unit notes 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is ?? 2: the x out pin is excluded. test conditions fig. 3.1.1 fig. 3.1.2 fig. 3.1.1 3.1.10 switching characteristics for system bus interface table 3.1.17 switching characteristics for system bus interface (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) after read data output enable time after read data output disable time after read obf 00 , obf 01 , obf 10 output propagation time t a (r-d) t v (r-d) t plh (r-obf) limits ns ns ns parameter min. typ. max. symbol unit 0 80 30 150 table 3.1.18 switching characteristics for system bus interface (2) (v cc =2.7 to 4.0 v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) after read data output enable time after read data output disable time after read obf 00 , obf 01 , obf 10 output propagation time t a (r-d) t v (r-d) t plh (r-obf) limits ns ns ns parameter min. typ. max. symbol unit 0 130 85 300
3886 group user? manual appendix 3.1 electrical characteristics 3-12 note: the reset out output goes ??in synchronized with the rise of the clock that is anywhere between a few cycles and 10-several cycles after reset input goes ?? table 3.1.19 timing requirements in memory expansion mode and microprocessor mode (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = ?0 to 85 ?, in high-speed mode, unless otherwise noted) onw input setup time onw input hold time data bus setup time data bus hold time onw input setup time onw input hold time data bus setup time data bus hold time t su (onw- ) t h ( -onw) t su (db- ) t h ( -db) t su (onw-rd), t su (onw-wr) t h (rd-onw), t h (wr-onw) t su (db-rd) t h (rd-db) limits ns ns ns ns ns ns ns ns parameter min. typ. max. symbol unit ?0 ?0 50 0 ?0 ?0 50 0 3.1.12 switching characteristics in memory expansion mode and microprocessor mode table 3.1.20 switching characteristics in memory expansion mode and microprocessor mode (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = ?0 to 85 ?, in high-speed mode, unless otherwise noted) clock cycle time clock ??pulse width clock ??pulse width ad 15 ?d 8 delay time ad 7 ?d 0 delay time ad 15 ?d 8 valid time ad 7 ?d 0 valid time sync delay time sync valid time data bus delay time data bus valid time rd pulse width, wr pulse width rd pulse width, wr pulse width (when one-wait is valid) ad 15 ?d 8 delay time ad 7 ?d 0 delay time ad 15 ?d 8 valid time ad 7 ?d 0 valid time data bus delay time data bus valid time reset out output delay time reset out output valid time (note) t c ( ) t wh ( ) t wl ( ) t d ( -ah) t d ( -al) t v ( -ah) t v ( -al) t d ( -sync) t v ( -sync) t d ( -db) t v ( -db) t wl (rd), t wl (wr) t d (ah-rd), t d (ah-wr) t d (al-rd), t d (al-wr) t v (rd-ah), t v (wr-ah) t v (rd-al), t v (wr-al) t d (wr-db) t v (wr-db) t d (reset-reset out ) t v ( -reset out ) limits parameter min. typ. max. symbol unit test conditions fig. 3.1.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t c (x in )?0 t c (x in )?0 2 2 10 t c (x in )?0 3t c (x in )?0 t c (x in )?5 t c (x in )?0 2 2 10 0 35 40 30 30 200 100 2t c (x in ) 16 20 5 5 16 5 15 t c (x in )?6 t c (x in )?0 5 5 15 3.1.11 timing requirements in memory expansion mode and microprocessor mode fig. 3.1.1 circuit for measuring output switching characteristics (1) fig. 3.1.2 circuit for measuring output switching characteristics (2) m e a s u r e m e n t o u t p u t p i n 1 0 0 p f c m o s o u t p u t n-channel open-drain outpu t m e a s u r e m e n t o u t p u t p i n 1 0 0 p f 1 k ?
3886 group user s manual appendix 3-13 3.1 electrical characteristics fig. 3.1.3 timing diagram (1) (in single-chip mode) 0 . 2 v c c t w l ( i n t ) 0 . 8 v c c t w h ( i n t ) 0 . 2 v c c 0.2v cc 0.8v cc 0.8v cc 0.2v cc t w l ( x i n ) 0 . 8 v c c t wh(x in) t c(x in ) x i n 0 . 2 v c c 0.8v cc t w(reset) reset t f t r 0.2v cc t wl(cntr) 0 . 8 v c c t w h ( c n t r ) t c ( c n t r ) t d ( s c l k 1 - t x d ) , t d ( s c l k 2 - s o u t 2 ) t v(s clk1 -t x d), t v(s clk2- s out2 ) t c ( s c l k 1 ) , t c ( s c l k 2 ) t wl(s clk1 ), t wl(s clk2 ) t wh(s clk1 ), t wh(s clk2 ) t h ( s c l k 1 - r x d ) , t h ( s c l k 2 - s i n 2 ) t su(r x d - s clk1 ), t su(s in2- s clk2 ) t x d s out2 r x d s i n 2 s c l k 1 s c l k 2 i n t 0 , i n t 1 i n t 2 0 , i n t 3 0 , i n t 4 0 i n t 2 1 , i n t 3 1 , i n t 4 1 c n t r 0 , c n t r 1 t i m i n g d i a g r a m i n s i n g l e - c h i p m o d e 0.2v cc t wl(x cin ) 0.8v cc t wh(x cin) t c(x cin ) x cin
3886 group user s manual appendix 3.1 electrical characteristics 3-14 fig. 3.1.4 timing diagram (2) (in memory expansion mode and microprocessor mode) t wl( ) 0.5v cc t wh( ) t c( ) t d ( - a h ) t d ( - a l ) t d ( - s y n c ) t v ( - a h ) t v ( - a l ) t v ( - s y n c ) t d ( - w r ) t v ( - w r ) 0 . 5 v c c 0 . 5 v c c 0 . 5 v c c 0 . 5 v c c t su(onw- ) t h( -onw) 0.8v cc 0.2v cc 0.8v cc 0.2v cc t s u ( d b - ) t h ( - d b ) 0.5v cc t d( -db) t v( -db) 0.2v cc 0 . 8 v c c 0 . 5 v c c t d(reset- reset out ) 0 . 5 v c c a d 1 5 a d 8 a d 7 a d 0 s y n c r d , w r onw d b 0 d b 7 db 0 db 7 reset r e s e t o u t t v ( - r e s e t o u t ) ( a t c p u r e a d i n g ) ( a t c p u w r i t i n g ) t i m i n g d i a g r a m i n m e m o r y e x p a n s i o n m o d e a n d m i c r o p r o c e s s o r m o d e ( 1 ) t i m i n g d i a g r a m i n m i c r o p r o c e s s o r m o d e
3886 group user s manual appendix 3-15 3.1 electrical characteristics fig. 3.1.5 timing diagram (3) (in memory expansion mode and microprocessor mode) 0 . 5 v c c r d , w r 0 . 5 v c c a d 1 5 a d 8 t d ( a h - w r ) t v ( w r - a h ) 0 . 5 v c c ad 7 ad 0 t d ( a l - w r ) t v(wr-al) 0 . 8 v c c 0.2v cc d b 0 d b 7 0.5v cc r d t s u ( d b - r d ) t h ( r d - d b ) 0.5v cc db 0 db 7 0 . 5 v c c wr t d ( w r - d b ) t v ( w r - d b ) t h ( w r - o n w ) 0 . 8 v c c 0 . 2 v c c o n w t s u ( o n w - w r ) t v ( r d - a h ) t d ( a h - r d ) t d ( a l - r d ) t v(rd-al) t h ( r d - o n w ) t s u ( o n w - r d ) t w l ( r d ) t w l ( w r ) (at cpu reading) ( a t c p u w r i t i n g ) t i m i n g d i a g r a m i n m e m o r y e x p a n s i o n m o d e a n d m i c r o p r o c e s s o r m o d e ( 2 )
3886 group user s manual appendix 3.1 electrical characteristics 3-16 fig. 3.1.6 timing diagram (4) (system bus interface) 0 . 4 5 ( 0 . 2 v c c ) 2 . 4 ( 0 . 8 v c c ) 0 . 4 5 ( 0 . 2 v c c ) 2 . 4 ( 0 . 8 v c c ) 0 . 4 5 ( 0 . 2 v c c ) 0 . 4 5 ( 0 . 2 v c c ) t s u ( a - r )t h ( r - a ) t s u ( s - r )t h ( r - s ) 0 . 4 5 ( 0 . 2 v c c ) 0 . 4 5 ( 0 . 2 v c c ) t w ( r ) 2 . 4 ( 0 . 8 v c c ) 2 . 4 ( 0 . 8 v c c ) 2.0 (0.8v cc ) 2.0 (0.8v cc ) 0 . 8 ( 0 . 2 v c c ) 0.8 (0.2v cc ) t a ( r - d ) t v ( r - d ) 0.8 (0.2v cc ) t p l h ( r - o b f ) a 0 r obf 00, obf 01, obf 10 0.45 (0.2v cc ) 2 . 4 ( 0 . 8 v c c ) 0.45 (0.2v cc ) 2 . 4 ( 0 . 8 v c c ) 0.45 (0.2v cc ) 0 . 4 5 ( 0 . 2 v c c ) t su (a-w) t h (w-a) t s u ( s - w )t h ( w - s ) 0.45 (0.2v cc ) 0 . 4 5 ( 0 . 2 v c c ) t w (w) 2.4 (0.8v cc ) 2 . 4 ( 0 . 8 v c c ) t s u ( d - w ) t h ( w - d ) a 0 w 0 . 4 5 ( 0 . 2 v c c ) 2 . 4 ( 0 . 8 v c c ) 0 . 4 5 ( 0 . 2 v c c ) 2.4 (0.8v cc ) s 0 , s 1 r e a d o p e r a t i o n write operation o u t s i d e o f p a r e n t h e s i s : t t l i / o inside of parenthesis : cmos i/o d q 0 d q 7 dq 0 dq 7 s 0 , s 1 s y s t e m b u s i n t e r f a c e t i m i n g d i a g r a m
3886 group user s manual appendix 3-17 3.1 electrical characteristics table 3.1.21 multi-master i 2 c-bus bus line characteristics fig. 3.1.7 timing diagram of multi-master i 2 c-bus 3.1.13 multi-master i 2 c-bus bus line characteristics symbol parameter unit bus free time hold time for start condition hold time for s cl clock = 0 rising time of both s cl and s da signals data hold time hold time for s cl clock = 1 falling time of both s cl and s da signals data setup time setup time for repeated start condition setup time for stop condition t buf t hd;sta t low t r t hd;dat t high t f t su;dat t su;sta t su;sto min. max. min. max. s s s ns s s ns ns s s standard clock mode high-speed clock mode note: c b = total capacitance of 1 bus line 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 300 0.9 300 t b u f t h d : s t a t h d : d a t t l o w t r t f t h i g h t s u : d a t t s u : s t a t hd:sta t s u : s t o s c l p s s r p s d a s: s t a r t c o n d i t i o n s r: r e s t a r t c o n d i t i o n p: s t o p c o n d i t i o n
3886 group user? manual appendix 3.2 standard characteristics 3-18 3.2 standard characteristics 3.2.1 power source current characteristic examples figure 3.2.1, figure 3.2.2, figure 3.2.3, figure 3.2.4, figure 3.2.5, figure 3.2.6 and figure 3.2.7 show power source current characteristic examples. fig. 3.2.1 power source current characteristic examples (in high-speed mode, a-d conversion and comparator operating) fig. 3.2.2 power source current characteristic examples (in high-speed mode) 0.0 v d d [ v ] i c c [ m a ] 2 . 53 . 03 . 54 . 04 . 55.05.5 2.0 4.0 6 . 0 8 . 0 10.0 1 2 . 0 1 4 . 0 1 6 . 0 6 . 0 : 1 0 m h z : 8 m h z : 4 m h z : 2 m h z : 5 0 0 k h z n o t e : e x t e r n a l c l o c k i n p u t [ m e a s u r i n g c o n d i t i o n : 2 5 c , i n h i g h - s p e e d m o d e , a - d c o n v e r s i o n a n d c o m p a r a t o r o p e r a t i n g ] 0 . 0 v d d [ v ] i c c [ m a ] 2.5 3 . 03.54 . 04.55.05 . 5 1 . 0 2 . 0 3 . 0 4 . 0 5.0 6 . 0 7 . 0 8 . 0 6 . 0 : 1 0 m h z : 8 m h z : 4 m h z : 2 m h z : 5 0 0 k h z n o t e : e x t e r n a l c l o c k i n p u t [measuring condition: 25 c, in high-speed mode]
3886 group user s manual appendix 3-19 3.2 standard characteristics fig. 3.2.3 power source current characteristic examples (in high-speed mode, wait execution) fig. 3.2.4 power source current characteristic examples (in middle-speed mode) 0.0 v d d [ v ] i c c [ m a ] 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 . 2 5 0.50 0.75 1.00 1 . 2 5 1 . 5 0 1 . 7 5 2 . 0 0 6.0 [ m e a s u r i n g c o n d i t i o n : 2 5 c , i n h i g h - s p e e d m o d e , w a i t e x e c u t i o n ] : 10mhz : 8mhz : 4mhz : 2mhz : 500khz note: external clock input 0 . 0 v d d [ v ] i c c [ m a ] 2 . 53 . 03 . 54 . 04.55 . 05.5 0 . 5 1.0 1.5 2.0 2 . 5 3 . 0 3 . 5 4 . 0 6 . 0 [ m e a s u r i n g c o n d i t i o n : 2 5 c , i n m i d d l e- s p e e d m o d e ] : 10mhz : 8mhz : 4mhz : 2mhz : 500khz note: external clock input
3886 group user s manual appendix 3.2 standard characteristics 3-20 fig. 3.2.5 power source current characteristic examples (in middle-speed mode, wait execution) fig. 3.2.6 power source current characteristic examples (in low-speed mode) 0.0 vdd [v] i c c [ m a ] 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 . 1 2 5 0.250 0.375 0.500 0 . 6 2 5 0 . 7 5 0 0 . 8 7 5 1 . 0 0 0 6.0 [ m e a s u r i n g c o n d i t i o n : 2 5 c , i n m i d d l e- s p e e d m o d e, w a i t e x e c u t i o n ] : 10mhz : 8mhz : 4mhz : 2mhz : 500khz note: external clock input 0 . 0 v d d [ v ] icc [ a] 2 . 53 . 03 . 54 . 04.55.05 . 5 1 0 . 0 20.0 30.0 40.0 5 0 . 0 6 0 . 0 7 0 . 0 8 0 . 0 6.0 : normal operation : wait instruction : normal operation (oscillator) : wait instruction (oscillator) [ m e a s u r i n g c o n d i t i o n : 2 5 c , i n l o w- s p e e d m o d e ]
3886 group user s manual appendix 3-21 3.2 standard characteristics fig. 3.2.7 power source current characteristic examples (at reset) 0.0 v d d [ v ] i c c [ m a ] 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 . 5 1.0 1.5 2.0 2 . 5 3 . 0 3 . 5 4 . 0 6.0 [ m e a s u r i n g c o n d i t i o n : 2 5 c , a t r e s e t ] : 10mhz : 8mhz : 4mhz : 2mhz : 500khz note: external clock input
3886 group user s manual appendix 3.2 standard characteristics 3-22 3.2.2 port standard characteristic examples figures 3.2.8, figures 3.2.9, figures 3.2.10, figures 3.2.11, figure 3.2.12, and figure 3.2.13 show port standard characteristic examples. fig. 3.2.8 standard characteristic examples of cmos output port at p-channel drive (ta=25 ?) fig. 3.2.9 standard characteristic examples of cmos output port at p-channel drive (ta=90 ?) 0 v oh [v] i o h [ m a ] 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 vcc=4.0v 5.5 v c c = 5 v vcc=2.7v 5 0 4 5 40 35 3 0 2 5 2 0 1 5 10 5 0 p o r t p 0 0 i o h - v o h c h a r a c t e r i s t i c s ( p - c h a n n e l d r i v e ) [ t a = 2 5 c ] ( p i n s w i t h s a m e c h a r a c t e r i s t i c : p 0 , p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 8 ) 0 v oh [v] i oh [ma] 0 . 51.0 1 . 52 . 02.53 . 03 . 54 . 04 . 55 . 0 v c c = 4 . 0 v 5 . 5 vcc=5v v c c = 2 . 7 v 5 0 4 5 40 3 5 30 2 5 2 0 1 5 1 0 5 0 port p0 0 i oh -v oh characteristics (p-channel drive) [ta=90 c] (pins with same characteristic: p0, p1, p2, p3, p4, p5, p6, p8)
3886 group user s manual appendix 3-23 3.2 standard characteristics fig. 3.2.10 standard characteristic examples of cmos output port at n-channel drive (ta=25 ?) fig. 3.2.11 standard characteristic examples of cmos output port at n-channel drive (ta=90 ?) 0 v ol [v] i o l [ m a ] 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5 1 0 1 5 2 0 2 5 30 3 5 4 0 4 5 5 0 vcc=4.0v 5.5 vcc=5v v c c = 2 . 7 v p o r t p 0 0 i o l - v o l c h a r a c t e r i s t i c s ( n - c h a n n e l d r i v e ) [ t a = 2 5 c ] ( p i n s w i t h s a m e c h a r a c t e r i s t i c : p 0 , p 1 , p 2 0 p 2 3 , p 3 , p 4 , p 5 , p 6 , p 7 , p 8 , a n d p 2 4 p 2 7 e x c e p t a t s i n g l e - c h i p m o d e ) 0 v o l [ v ] i o l [ m a ] 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 vcc=4.0v 5.5 vcc=5v v c c = 2 . 7 v port p0 0 i ol -v ol characteristics (n-channel drive) [ta=90 c] (pins with same characteristic: p0, p1, p2 0 p2 3 , p3, p4, p5, p6, p7, p8, and p2 4 p2 7 except at single-chip mode)
3886 group user s manual appendix 3.2 standard characteristics 3-24 fig. 3.2.12 standard characteristic examples of cmos large current output port at n-channel drive (ta=25 ?) fig. 3.2.13 standard characteristic examples of cmos large current output port at n-channel drive (ta=90 ?) 0 v ol [v] i o l [ m a ] 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 0 2 0 3 0 4 0 5 0 60 7 0 8 0 9 0 1 0 0 vcc=4.0v 5.5 v c c = 5 v vcc=2.7v p o r t p 2 4 i o l - v o l c h a r a c t e r i s t i c s ( n - c h a n n e l d r i v e ) [ t a = 2 5 c ] ( p i n s w i t h s a m e c h a r a c t e r i s t i c : p 2 4 p 2 7 a t s i n g l e - c h i p m o d e ) 0 v ol [v] i ol [ma] 0 . 5 0 1 . 01.52.02 . 53 . 03 . 54.04 . 55 . 0 1 0 2 0 3 0 4 0 5 0 60 7 0 8 0 9 0 1 0 0 v c c = 4 . 0 v 5.5 v c c = 5 v vcc=2.7v port p2 4 i ol -v ol characteristics (n-channel drive) [ta=90 c] (pins with same characteristic: p2 4 p2 7 at single-chip mode)
3886 group user s manual appendix 3-25 3.2 standard characteristics fig. 3.2.14 standard characteristic examples of cmos input port at pull-up (ta=25 ?) fig. 3.2.15 standard characteristic examples of cmos input port at pull-up (ta=90 ?) 3.2.3 input port standard characteristic examples figures 3.2.14 and figure 3.2.15 show port standard characteristic examples. 0 v il [v] i i l [ a ] 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 0 20 3 0 4 0 5 0 60 7 0 8 0 9 0 1 0 0 v c c = 4 . 0 v 5.5 vcc=5v v c c = 2 . 7 v p o r t p 3 0 i il - v il c h a r a c t e r i s t i c s ( a t p u l l - u p ) [ t a = 2 5 c ] ( p i n s w i t h s a m e c h a r a c t e r i s t i c : p 3 ) 0 v il [v] i i l [ a ] 0 . 5 0 1.0 1.5 2 . 02.53 . 03 . 54 . 04 . 55 . 0 1 0 2 0 3 0 4 0 5 0 60 7 0 8 0 9 0 1 0 0 v c c = 4 . 0 v 5.5 v c c = 5 v vcc=2.7v port p3 0 i il -v il characteristics (at pull-up) [ta=90 c] (pins with same characteristic: p3)
3886 group user s manual appendix 3.2 standard characteristics 3-26 3.2.4 a-d conversion standard characteristics figure 3.2.16 shows the a-d conversion standard characteristics. fig. 3.2.16 a-d conversion standard characteristics 1 5 1 0 5 - 5 - 1 0 - 1 5 0 e r r o r [ m v ] s t e p n o . 01 63 24 86 48 0961 1 21281 4 41 6 01761 9 22 0 82242 4 02 5 6 0 . 0 5.0 1 0 . 0 1 5 . 0 1 l s b w i d t h [ m v ] 1 5 1 0 5 - 5 -10 -15 0 e r r o r [ m v ] step no. 256 0 . 0 5 . 0 1 0 . 0 1 5 . 0 1 l s b w i d t h [ m v ] 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 512 1 5 10 5 -5 - 1 0 -15 0 e r r o r [ m v ] s t e p n o . 5 1 2 0 . 0 5 . 0 1 0 . 0 1 5 . 0 1 l s b w i d t h [ m v ] 5 2 8 5 4 45 6 05 7 65926 0 66 2 46406 5 66 7 26887 0 47 2 07367 5 27 6 8 1 5 1 0 5 -5 - 1 0 - 1 5 0 e r r o r [ m v ] step no. 7 6 8 0.0 5 . 0 1 0 . 0 1 5 . 0 1 l s b w i d t h [ m v ] 7 8 4 8 0 08 1 68 3 28488 6 48 8 08969 1 29 2 89449 6 09 7 6 992 1008 1 0 2 4 3 8 8 6 g r o u p a - d c o n v e r t e r e r r o r & s t e p w i d t h m e a s u r e m e n t v c c = 5 . 1 2 [ v ] , v r e f = 5 . 1 2 [ v ] x i n = 8 [ m h z ] , t e m p = 2 5 [ d e g . ] 1 l s b w i d t h e r r o r ( a b s o l u t e p r e c i s i o n e r r o r )
3886 group user s manual appendix 3-27 3.2 standard characteristics 3.2.5 d-a conversion standard characteristics figure 3.2.17 shows the d-a conversion standard characteristics. fig. 3.2.17 d-a conversion standard characteristics 3 0 2 0 10 - 1 0 - 2 0 -30 0 e r r o r [ m v ] step no. 01 63 248 648 09 61 1 21 2 8 3 0 20 1 0 - 1 0 - 2 0 -30 0 e r r o r [ m v ] step no. 128 1 4 41 6 01 7 61922 0 82242 4 02 5 6 3 8 8 6 g r o u p d - a c o n v e r t e r e r r o r & s t e p w i d t h m e a s u r e m e n t vcc = 5.12 [v], v ref = 5.12 [v] x in = 8 [mhz], temp = 25 [deg.]
3886 group user? manual 3.3 notes on use 3.3 notes on use 3.3.1 notes on input and output pins (1) notes in stand-by state in stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an i/o port ?ndefined? especially for i/o ports of the n-channel open-drain. pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: ?external circuit ?variation of output levels during the ordinary operation when using built-in pull-up or pull-down resistor, note on varied current values: ?when setting as an input port : fix its input level when setting as an output port : prevent current from flowing out to external reason in i/o ports of the n-channel open-drain, in spite of setting as an output port with its direction register, when the content of the port latch is ?? the transistor becomes the off state, which causes the ports to be the high-impedance state. note that the level becomes ?ndefined?depending on external circuits. accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input port and an i/o port are ?ndefined? this may cause power source current. * 1 stand-by state : the stop mode by executing the stp instruction the wait mode by executing the wit instruction (2) modifying output data with bit managing instruction when the port latch of an i/o port is modified with the bit managing instruction* 2 , the value of the unspecified bit may be changed. reason the bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the port latch of an i/o port, the following is executed to all bits of the port latch. ?as for a bit which is set for an input port : the pin state is read in the cpu, and is written to this bit after bit managing. ?as for a bit which is set for an output port : the bit value of the port latch is read in the cpu, and is written to this bit after bit managing. note the following : ?even when a port which is set as an output port is changed for an input port, its port latch holds the output data. ?as for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. * 2 bit managing instructions : seb , and clb instructions
3886 group user? manual 3-29 appendix 3.3 notes on use 3.3.2 termination of unused pins (1) terminate unused pins ? output ports : open ? input ports : connect each pin to v cc or v ss through each resistor of 1 k ? to 10 k ? . with regard to ports which can select the built-in pull-up resistor, the built-in pull-up resistor can be used. as for pins whose potential affects to operation modes such as the cnv ss pin or others, select the v cc pin or the v ss pin according to their operation mode. ? i/o ports : ?set the i/o ports for the input mode and connect them to v cc or v ss through each resistor of 1 k ? to 10 k ? . with regard to ports which can select the built-in pull-up resistor, the built-in pull- up resistor can be used. set the i/o ports for the output mode and open them at ??or ?? ?when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the system, thoroughly perform system evaluation on the user side. ?since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. ? the avss pin when not using the a-d/d-a converter : ?when not using the a-d/d-a converter, handle a power source pin for the a-d/d-a converter, avss pin as follows: ?avss: connect to the vss pin (2) termination remarks ? input ports and i/o ports : do not open in the input mode. reason ?the power source current may increase depending on the first-stage circuit. ?an effect due to noise may be easily produced as compared with proper termination ? and ? shown on the above. ? i/o ports : when setting for the input mode, do not connect to v cc or v ss directly. reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and v cc (or v ss ).
3886 group user? manual 3.3 notes on use (2) check of interrupt request bit when executing the bbc or bbs instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to ??by using a data transfer instruction, execute one or more instructions before executing the bbc or bbs instruction. ? i/o ports : when setting for the input mode, do not connect multiple ports in a lump to v cc or v ss through a resistor. reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. ?at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. 3.3.3 notes on interrupts (1) switching external interrupt detection edge when switching the external interrupt detection edge, switch it in the following sequence. clear an interrupt enable bit to ??(interrupt disabled) switch the detection edge clear an interrupt request bit to ? (no interrupt request issued) set the interrupt enable bit to ??(interrupt enabled) fig. 3.3.1 sequence of switching the detection edge reason the interrupt circuit recognizes the switching of the detection edge as the change of external input signals. this may cause an unnecessary interrupt. clear the interrupt request bit to ??(no interrupt issued) nop (one or more instructions) execute the bbc or bbs instruction data transfer instruction: ldm, lda, sta, stx, and sty instructions fig. 3.3.2 sequence of check of interrupt request bit
3886 group user? manual 3-31 appendix 3.3 notes on use reason if the bbc or bbs instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to ?? the value of the interrupt request bit before being cleared to ? is read. (3) change of relevant register setting when the setting of the following register or bit is changed, the interrupt request bit may be set to ?? ?nterrupt edge selection register (address 3a 16 ) ?nterrupt source selection register (address 39 16 ) ?nt2, int3, int4 interrupt switch bit of port control register 2 (bit 4 of address 2f 16 ) set the above listed registers or bits as the following sequence. clear an interrupt enable bit to ??(interrupt disabled) set the above listed registers or bits clear an interrupt request bit to ? (no interrupt request issued) set the interrupt enable bit to ??(interrupt enabled) fig. 3.3.3 sequence of changing relevant register 3.3.4 notes on timer if a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). when switching the count source by the timer y count source selection bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. therefore, select the timer count source before set the value to the timer.
3886 group user? manual 3.3 notes on use 3.3.5 notes on serial i/o (1) notes when selecting clock synchronous serial i/o (serial i/o1) ? stop of transmission operation clear the serial i/o1 enable bit and the transmit enable bit to ??(serial i/o1 and transmit disabled). reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to ??(serial i/o1 disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to ??at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. ? stop of receive operation clear the receive enable bit to ??(receive disabled), or clear the serial i/o1 enable bit to ? (serial i/o1 disabled). ? stop of transmit/receive operation clear both the transmit enable bit and receive enable bit to ??(transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial i/o mode, any one of data transmission and reception cannot be stopped.) reason in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also operates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to ??(transmit disabled). also, the transmission circuit is not initialized by clearing the serial i/o1 enable bit to ??(serial i/o1 disabled) (refer to (1) ? ).
3886 group user? manual 3-33 appendix 3.3 notes on use (2) notes when selecting clock asynchronous serial i/o (serial i/o1) ? stop of transmission operation clear the transmit enable bit to ??(transmit disabled). reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to ??(serial i/o1 disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to ??at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. ? stop of receive operation clear the receive enable bit to ??(receive disabled). ? stop of transmit/receive operation only transmission operation is stopped. clear the transmit enable bit to ??(transmit disabled). reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to ??(serial i/o1 disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to ??at this time, the data during internally shifting is output to the txd pin and an operation failure occurs. only receive operation is stopped. clear the receive enable bit to ??(receive disabled). (3) s rdy1 output of reception side (serial i/o1) when signals are output from the s rdy1 pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy1 output enable bit, and the transmit enable bit to ??(transmit enabled). (4) setting serial i/o1 control register again (serial i/o1) set the serial i/o1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to ?. fig. 3.3.4 sequence of setting serial i/o1 control register again clear both the transmit enable bit (te) and the receive enable bit (re) to ? set the bits 0 to 3 and bit 6 of the serial i/o control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to ? can be set with the ldm instruction at the same time
3886 group user? manual 3.3 notes on use (5) data transmission control with referring to transmit shift register completion flag (serial i/o1) the transmit shift register completion flag changes from ??to ??with a delay of 0.5 to 1.5 shift clocks after writing the data to the transmit buffer register. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. (6) transmission control when external clock is selected (serial i/o1) when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to ??at ??of the s clk input level. also, write the transmit data to the transmit buffer register (serial i/o shift register) at ??of the s clk input level. (7) transmit interrupt request when transmit enable bit is set (serial i/o1) when the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown in the following sequence. ? set the interrupt enable bit to ??(disabled) with clb instruction. ? prepare serial i/o for transmission/reception. ? set the interrupt request bit to ??with clb instruction after 1 or more instruction has been executed. ? set the interrupt enable bit to ??(enabled). reason when the transmission enable bit is set to ?? the transmit buffer empty flag and transmit shift register completion flag are set to ?? the interrupt request is generated and the transmission interrupt bit is set regardless of which of the two timings listed below is selected as the timing for the transmission interrupt to be generated. ?transmit buffer empty flag is set to ? ?transmit shift register completion flag is set to ? (8) transmit data writing (serial i/o2) in the clock synchronous serial i/o, when selecting an external clock as synchronous clock, write the transmit data to the serial i/o2 register (serial i/o shift register) at ??of the transfer clock input level.
3886 group user? manual 3-35 appendix 3.3 notes on use 3.3.6 notes on multi-master i 2 c-bus interface (1) read-modify-write instruction precautions for read-modify-write instructions, such as seb and clb , when used for any of the registers of the multi-master i 2 c-bus interface, are described below. ? i 2 c data shift register (s0: address 0012 16 ) when executing the read-modify-write instruction for this register during transfer, data may become an unexpected value. ? i 2 c address register (s0d: address 0013 16 ) when the read-modify-write instruction is executed for this register at detecting the stop condition, data may become an unexpected value. reason because hardware changes the read/write bit (rwb) at detecting the stop condition. ? i 2 c status register (s1: address 0014 16 ) do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. ? i 2 c control register (s1d: address 0015 16 ) when the read-modify-write instruction is executed for this register at detecting the start condition or at completing the byte transfer, data may become an unexpected value. reason because hardware changes the bit counter (bc0 to bc2). ? i 2 c clock control register (s2: address 0016 16 ) the read-modify-write instruction can be executed for this register. ? i 2 c start/stop condition control register (s2d: address 0017 16 ) the read-modify-write instruction can be executed for this register. (2) procedure for generating start condition using multi-master ? procedure example (the necessary conditions for the procedure are described in items ? to ? below). lda #sladr (take out slave address value) sei (disable interrupt) bbs 5, s1, busbusy (bb flag confirmation and branch process) busfree: sta s0 (write slave address value) ldm #$f0, s1 (trigger start condition generation) cli (enable interrupt) : : busbusy: cli (enable interrupt) : : ? use ?ranch on bit set?of ?bs 5, s1, for the bb flag confirmation and branch process. ? use ?ta? ?tx?or ?ty?of the zero page addressing instruction for writing the slave address value to the i 2 c data shift register (s0: address 0012 16 ). ? execute the branch instruction of above ? and the store instruction of above ? continuously shown the above procedure example. ? disable interrupts during the following three process steps: ?bb flag confirmation ?write slave address value ?trigger start condition generation when the bb flag is in bus busy state, enable interrupts immediately.
3886 group user? manual 3.3 notes on use (3) procedure for generating restart condition this procedure cannot be applied to m3886 7m8a and m3886 7e8a when the external memory is used and the bus cycle is extended by onw function. ? procedure example (the necessary conditions for the procedure are described in items ? to ? below). execute the following procedure when the pin bit is ?? ldm #$00, s1 (select slave receive mode) lda #sladr (take out slave address value) sei (disable interrupt) sta s0 (write slave address value) ldm #$f0, s1 (trigger restart condition generation) cli (enable interrupt) : : ? select the slave receive mode when the pin bit is ?? do not write ??to the pin bit. neither ??nor ??is specified as input to the bb bit. the trx bit becomes ??and the sda pin is released. ? the scl pin is released by writing the slave address value to the i 2 c data shift register. ? disable interrupts during the following two process steps: ?write slave address value ?trigger restart condition generation (4) writing to i 2 c status register do not execute an instruction to set the pin bit to ??from ??and an instruction to set the mst and trx bits to ??from ??simultaneously. because it may enter the state that the scl pin is released and the sda pin is released after about one machine cycle. do not execute an instruction to set the mst and trx bits to ??from ??simultaneously when the pin bit is ?? because it may become the same as above. (5) process of after stop condition generating do not write data in the i 2 c data shift register (s0) and the i 2 c status register (s1) until the bus busy flag bb becomes ??after generating the stop condition in the master mode. because the stop condition waveform might not be normally generated. reading to the above registers does not have the problem. (6) stop condition input at 7th clock pulse the sda line may be held at low even if flag bb is set to ??when all the following conditions are satisfied: ?he stop condition is input at the 7th clock pulse while receiving a slave address or data. ?he clock pulse is continuously input. ?n the slave mode countermeasure: write dummy data to the i 2 c shift register or reset the es0 bit in the s1d register (es0 = ?? es0 = ?? during a stop condition interrupt routine with flag pin = ?? note: do not use the read-modify-write instruction at this time. furthermore, when the es0 bit is set to ?? the sda pin becomes a general-purpose port ; so that the port must be set to input mode or output ?? (7) es0 bit switch in standard clock mode when ssc = ?0010 2 ?or in high-speed clock mode, flag bb may switch to ??if es0 bit is set to ??when sda is ?? countermeasure: set es0 to 1 when sda is h .
3886 group user? manual 3-37 appendix 3.3 notes on use 3.3.8 notes on a-d converter (1) analog input pin make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 f to 1 f. further, be sure to verify the operation of application products on the user side. reason an analog input pin includes the capacitor for analog voltage comparison. accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. this may cause the a-d conversion precision to be worse. (2) a-d converter power source pin the av ss pin is an a-d converter power source pin. regardless of using the a-d conversion function or not, connect them as following : ?av ss : connect to the v ss line reason if the av ss pin is opened, the microcomputer may have a failure because of noise or others. (3) clock frequency during a-d conversion the comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. thus, make sure the following during an a-d conversion. ?f(x in ) is 500 khz or more ?do not execute the stp instruction 3.3.9 notes on d-a converter (1) vcc when using d-a converter the d-a converter accuracy when vcc is 4.0 v or less differs from that of when vcc is 4.0 v or more. when using the d-a converter, we recommend using a vcc of 4.0 v or more. (2) d-ai conversion register when not using d-a converter when a d-a converter is not used, set all values of the d-ai conversion registers (i = 1, 2) to ?0 16 ? the initial value after reset is ?0 16 ? 3.3.7 notes on pwm for pwm 0 output, ??level is output first. after data is set to the pwm0l and the pwm0h registers, pwm waveform corresponding to the new data is output from next repetitive period. fig. 3.3.5 pwm 0 output pwm 0 output data is updated. updated data is output from next repetitive period.
3886 group user? manual 3.3 notes on use 3.3.10 notes on watchdog timer make sure that the watchdog timer does not underflow while waiting stop release, because the watchdog timer keeps counting during that term. when the stp instruction disable bit has been set to 1 , it is impossible to switch it to 0 by a program. 3.3.11 notes on reset pin (1) connecting capacitor in case where the reset signal rise time is long, connect a ceramic capacitor or others across the reset pin and the v ss pin. use a 1000 pf or more capacitor for high frequency use. when connecting the capacitor, note the following : ?make the length of the wiring which is connected to a capacitor as short as possible. ?be sure to verify the operation of application products on the user side. reason if the several nanosecond or several ten nanosecond impulse noise enters the reset pin, it may cause a microcomputer failure. 3.3.12 notes on cpu reprogramming mode (1) transfer the cpu reprogramming mode control program to the internal ram before selecting the cpu reprogramming mode, and then, execute it on the internal ram. additionally, when the subroutine or stack operation instruction is used in the control program, make sure the control program is not destroyed by the stack operation. (2) make sure each instruction description (specified address etc.) is correct, because the cpu reprogramming mode control program is transferred to the internal ram and executed on the internal ram. (3) in order to avoid generation of a watchdog timer reset, write to the watchdog timer control register periodically during the cpu reprogramming mode control program (refer to ?.7 watchdog timer?. (4) notes on flash memory version the cnv ss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it works as a program power source pin (v pp pin), as well. to improve the noise margin, connect the cnv ss pin to v ss through 1 to 10 k ? resistor. when the cnv ss pin of the mask rom version is connected to vss through this resistor, the function of mask rom version works well in the same manner as flash memory version. 3.3.13 notes on using stop mode clock restoration after restoration to the normal mode from the stop mode by an interrupt request, the contents of the cpu mode register previous to the stp instruction execution are retained. accordingly, if both main clock and sub clock were oscillating before execution of the stp instruction, the oscillation of both clocks is resumed at restoration. in the above case, when the main clock side is set as a system clock, the oscillation stabilizing time for approximately 8,000 cycles of the x in input is reserved at restoration from the stop mode. at this time, note that the oscillation on the sub clock side may not be stabilized even after the lapse of the oscillation stabilizing time of the main clock side.
3886 group user? manual 3-39 appendix 3.3 notes on use fig. 3.3.6 ceramic resonator circuit 3.3.14 notes on wait mode clock restoration if the wait mode is released by a reset when x cin is set as the system clock and x in oscillation is stopped during execution of the wit instruction, x cin oscillation stops, x in oscillation starts, and x in is set as the system clock. in the above case, the reset pin should be held at ??until the oscillation is stabilized. 3.3.15 notes on low-speed operation mode (1) using sub-clock to use a sub-clock, fix bit 3 of the cpu mode register to ??and control the rd (refer to figure 3.3.6) resistance value to a certain level to stabilize an oscillation. for resistance value of rd, consult the oscillator manufacturer. reason when the bit 3 of the cpu mode register is set to ?? the sub-clock oscillation may stop. 3.3.16 notes on restarting oscillation (1) restarting oscillation usually, when the mcu stops the clock oscillation by stp instruction and the stp instruction has been released by an external interrupt source, the fixed values of timer 1 and prescaler 12 (timer 1 = 01 16 , prescaler 12 = ff 16 ) are automatically reloaded in order for the oscillation to stabilize. the user can inhibit the automatic setting by writing ??to bit 6 of the port control register 2 (address 002f 16 ). however, by setting this bit to ?? the previous values, set just before the stp instruction was executed, will remain in timer 1 and prescaler 12. therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the stp instruction. reason oscillation will restart when an external interrupt is received. however, internal clock phi is supplied to the cpu only when timer 1 underflows. this ensures time for the clock oscillation using the ceramic resonators to be stabilized. r d c cin c cout x c i n x cout r f
3886 group user? manual 3.3 notes on use fig. 3.3.9 stack memory contents after php instruction execution plp instruction execution nop fig. 3.3.8 sequence of plp instruction execution ( s ) ( s ) + 1 s t o r e d p s 3.3.17 notes on programming (1) processor status register ? initializing of processor status register flags which affect program execution must be initialized after a reset. in particular, it is essential to initialize the t and d flags because they have an important effect on calculations. reason after a reset, the contents of the processor status register (ps) are undefined except for the i flag which is ?? reset initializing of flags main program fig. 3.3.7 initialization of processor status register ? how to reference the processor status register to reference the contents of the processor status register (ps), execute the php instruction once then read the contents of (s+1). if necessary, execute the plp instruction to return the ps to its original status. a nop instruction should be executed after every plp instruction.
3886 group user? manual 3-41 appendix 3.3 notes on use (2) brk instruction ? detection of interrupt source it can be detected that the brk instruction interrupt event or the least priority interrupt event by referring the stored b flag state. refer to the stored b flag state in the interrupt routine. ? interrupt priority level when the brk instruction is executed with the following conditions satisfied, the interrupt execution is started from the address of interrupt vector which has the highest priority. ?interrupt request bit and interrupt enable bit are set to ?? ?interrupt disable flag (i) is set to ??to disable interrupt. (3) decimal calculations ? execution of decimal calculations the adc and sbc are the only instructions which will yield proper decimal notation, set the decimal mode flag (d) to ??with the sed instruction. after executing the adc or sbc instruction, execute another instruction before executing the sec , clc , or cld instruction. ? notes on status flag in decimal mode when decimal mode is selected, the values of three of the flags in the status register (the n, v, and z flags) are invalid after a adc or sbc instruction is executed. the carry flag (c) is set to ??if a carry is generated as a result of the calculation, or is cleared to ??if a borrow is generated. to determine whether a calculation has generated a carry, the c flag must be initialized to ??before each calculation. to check for a borrow, the c flag must be initialized to ??before each calculation. fig. 3.3.10 interrupt routine (s) ( s ) + 1 p c l ( l o w - o r d e r o f p r o g r a m c o u n t e r ) 74 0 1 = b f l a g p c h ( h i g h - o r d e r o f p r o g r a m c o u n t e r ) ps ( s ) + 2 ( s ) + 3 set d flag to ? adc or sbc instruction nop instruction sec , clc , or cld instruction fig. 3.3.11 status flag at decimal calculations
3886 group user? manual 3.3 notes on use (4) jmp instruction when using the jmp instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 3.3.18 programming and test of built-in prom version as for in the one time prom version (shipped in blank) and the built-in eprom version, their built-in prom can be read or programmed with a general-purpose prom programmer using a special programming adapter. the built-in eprom version is available only for program development and on-chip program evaluation. the programming test and screening for prom of the one time prom version (shipped in blank) are not performed in the assembly process and the following processes. to ensure reliability after programming, performing programming and test according to the figure 3.3.12 before actual use are recommended. fig. 3.3.12 programming and testing of one time prom version programming with prom programmer screening (caution) (leave at 150 c for 40 hours) v e r i f i c a t i o n w i t h p r o m p r o g r a m m e r f u n c t i o n a l c h e c k i n t a r g e t d e v i c e caution: t h e s c r e e n i n g t e m p e r a t u r e i s f a r h i g h e r t h a n t h e s t o r a g e t e m p e r a t u r e . n e v e r e x p o s e t o 1 5 0 c e x c e e d i n g 1 0 0 h o u r s .
3886 group user? manual 3-43 appendix 3.3 notes on use 3.3.19 notes on built-in prom version (1) programming adapter use a special programming adapter shown in table 3.3.1 and a general-purpose prom programmer when reading from or programming to the built-in prom in the built-in prom version. table 3.3.1 programming adapters m3886 7e8afs m3886 7e8ahp (one time prom version shipped in blank) programming adapter pca4738l-80a pca4738h-80a microcomputer (2) programming/reading in prom mode, operation is the same as that of the m5m27c101ak, but programming conditions of prom programmer are not set automatically because there are no internal device id codes. accurately set the following conditions for data programming/reading. take care not to apply 21 v to v pp pin (is also used as the cnv ss pin), or the product may be permanently damaged. ?programming voltage: 12.5 v ?setting of prom programmer switch: refer to table 3.3.2. product name format prom programmer start address address 08080 16 prom programmer end address m3886 7e8afs m3886 7e8ahp table 3.3.2 prom programmer address setting address 0fffd 16 note: addresses 8080 16 to fffd 16 in the built-in prom corresponds to addresses 08080 16 to 0fffd 16 in the prom programmer. (3) erasing contents of the windowed eprom are erased through an ultraviolet light source of the wavelength 2537 ?ngstrom. at least 15 w ?sec/cm 2 are required to erase eprom contents.
3886 group user? manual 3.4 countermeasures against noise fig. 3.4.1 wiring for the reset pin 3.4 countermeasures against noise countermeasures against noise are described below. the following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 shortest wiring length (1) wiring for reset pin make the length of wiring which is connected to the reset pin as short as possible. especially, connect a capacitor across the reset pin and the v ss pin with the shortest possible wiring (within 20mm). reason the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the reset pin, the reset is released before the internal state of the microcomputer is completely initialized. this may cause a program runaway. (2) wiring for clock input/output pins ?make the length of wiring which is connected to clock i/o pins as short as possible. ?make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. ?separate the v ss pattern only for oscillation from other v ss patterns. reason if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the microcomputer. fig. 3.4.2 wiring for clock i/o pins reset r e s e t c i r c u i t n o i s e v ss v s s r e s e t c i r c u i t v ss reset v ss n.g. o.k. n o i s e x in x o u t v ss x in x o u t v ss n.g. o.k.
3886 group user s manual 3-45 appendix 3.4 countermeasures against noise fig. 3.4.4 wiring for the v pp pin of the one time prom version and the eprom version (3) wiring to cnv ss pin connect the cnv ss pin to the v ss pin with the shortest possible wiring. reason the processor mode of a microcomputer is influenced by a potential at the cnv ss pin. if a potential difference is caused by the noise between pins cnv ss and v ss , the processor mode may become unstable. this may cause a microcomputer malfunction or a program runaway. fig. 3.4.3 wiring for cnv ss pin (4) wiring to v pp pin of one time prom version and eprom version connect an approximately 5 k ? resistor to the v pp pin the shortest possible in series and also to the v ss pin. when not connecting the resistor, make the length of wiring between the v pp pin and the v ss pin the shortest possible. note: even when a circuit which included an approximately 5 k ? resistor is used in the mask rom version, the microcomputer operates correctly. reason the v pp pin of the one time prom and the eprom version is the power source input pin for the built-in prom. when programming in the built-in prom, the impedance of the v pp pin is low to allow the electric current for writing flow into the prom. because of this, noise can enter easily. if noise enters the v pp pin, abnormal instruction codes or data are read from the built-in prom, which may cause a program runaway. n o i s e c n v s s v s s c n v s s v s s n.g. o . k . c n v s s / v p p v s s in the shortest distance a p p r o x i m a t e l y 5 k ?
3886 group user s manual 3.4 countermeasures against noise fig. 3.4.5 bypass capacitor across the v ss line and the v cc line 3.4.2 connection of bypass capacitor across v ss line and v cc line connect an approximately 0.1 f bypass capacitor across the v ss line and the v cc line as follows: connect a bypass capacitor across the v ss pin and the v cc pin at equal length. connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. use lines with a larger diameter than other signal lines for v ss line and v cc line. connect the power source wiring via a bypass capacitor to the v ss pin and the v cc pin. 3.4.3 wiring to analog input pins connect an approximately 100 ? to 1 k ? resistor to an analog signal line which is connected to an analog input pin in series. besides, connect the resistor to the microcomputer as close as possible. connect an approximately 1000 pf capacitor across the v ss pin and the analog input pin. besides, connect the capacitor to the v ss pin as close as possible. also, connect the capacitor across the analog input pin and the v ss pin at equal length. reason signals which is input in an analog input pin (such as an a-d converter/comparator input pin) are usually output signals from sensor. the sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. this long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. if a capacitor between an analog input pin and the v ss pin is grounded at a position far away from the v ss pin, noise on the gnd line may enter a microcomputer through the capacitor. fig. 3.4.6 analog signal line and a resistor and a capacitor v s s v c c v s s v cc n.g. o.k. analog input pin v s s n o i s e thermisto r microcomputer n.g. o . k . ( n o t e ) n o t e : t h e r e s i s t o r i s u s e d f o r d i v i d i n g r e s i s t a n c e w i t h a t h e r m i s t o r .
3886 group user s manual 3-47 appendix 3.4 countermeasures against noise (2) installing oscillator away from signal lines where potential levels change frequently install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. reason signal lines where potential levels change frequently (such as the cntr pin signal line) may affect other lines at signal rising edge or falling edge. if such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. fig. 3.4.8 wiring of reset pin 3.4.4 oscillator concerns take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) keeping oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. reason in the system using a microcomputer, there are signal lines for controlling motors, leds, and thermal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual inductance. fig. 3.4.7 wiring for a large current signal line x in x out v ss m microcomputer m u t u a l i n d u c t a n c e l a r g e c u r r e n t gnd x in x o u t v s s cntr d o n o t c r o s s n.g.
3886 group user s manual 3.4 countermeasures against noise (3) oscillator protection using v ss pattern as for a two-sided printed circuit board, print a v ss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. connect the v ss pattern to the microcomputer v ss pin with the shortest possible wiring. besides, separate this v ss pattern from other v ss patterns. fig. 3.4.9 v ss pattern on the underside of an oscillator fig. 3.4.10 setup for i/o ports 3.4.5 setup for i/o ports setup i/o ports using hardware and software as follows: connect a resistor of 100 ? or more to an i/o port in series. as for an input port, read data several times by a program for checking whether input levels are equal or not. as for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. rewrite data to direction registers at fixed periods. note: when a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. if this is undesirable, connect a capacitor to this port to remove the noise pulse. x in x out v ss a n e x a m p l e o f v s s p a t t e r n s o n t h e u n d e r s i d e o f a p r i n t e d c i r c u i t b o a r d o s c i l l a t o r w i r i n g p a t t e r n e x a m p l e s e p a r a t e t h e v s s l i n e f o r o s c i l l a t i o n f r o m o t h e r v s s l i n e s direction register port latch data bus i/o port pins noise noise n.g. o.k.
3886 group user s manual 3-49 appendix 3.4 countermeasures against noise 3.4.6 providing of watchdog timer function by software if a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. this is equal to or more effective than program runaway detection by a hardware watchdog timer. the following shows an example of a watchdog timer provided by software. in the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. this example assumes that interrupt processing is repeated multiple times in a single main routine processing. assigns a single byte of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main routine. the initial value n should satisfy the following condition: n+1 ( counts of interrupt processing executed in each main routine) as the main routine execution cycle may change because of an interrupt processing or others, the initial value n should have a margin. watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt processing after the initial value n has been set. detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents do not change after interrupt processing. decrements the swdt contents by 1 at each interrupt processing. determines that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed interrupt processing count). detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents are not initialized to the initial value n but continued to decrement and if they reach 0 or less. fig. 3.4.11 watchdog timer by software main routine (swdt) n cli main processing (swdt) interrupt processing routine errors n interrupt processing routine (swdt) (swdt) 1 interrupt processing (swdt) main routine errors > 0 0 rti return =n? 0? n
3886 group user? manual 3-50 appendix 3.5 list of registers 3.5 list of registers fig. 3.5.1 structure of port pi fig. 3.5.2 structure of port pi direction register port pi b 7b6b 5b 4b 3b 2b 1b 0 bf u n c t i o n a t r e s e t r w 0 1 2 3 4 5 6 7 n a m e p o r t p i 0 p o r t p i 1 p o r t p i 2 port pi 3 p o r t p i 4 p o r t p i 5 p o r t p i 6 p o r t p i 7 i n o u t p u t m o d e w r i t e r e a d port latch i n i n p u t m o d e w r i t e : p o r t l a t c h r e a d : v a l u e o f p i n s p o r t p i ( p i ) ( i = 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 ) [ a d d r e s s : 0 0 1 6 , 0 2 1 6 , 0 4 1 6 , 0 6 1 6 , 0 8 1 6 , 0 a 1 6 , 0 c 1 6 , 0 e 1 6 , 1 0 1 6 ] u n d e f i n e d u n d e f i n e d u n d e f i n e d undefined u n d e f i n e d u n d e f i n e d undefined undefined port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi direction register 0 0 0 0 0 0 0 0 port pi direction register (pid) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8) [address : 01 16 , 03 16 , 05 16 , 07 16, 09 16 , 0b 16 , 0d 16 , 0f 16 , 11 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ? ? ? ? ? ? ? ?
3886 group user s manual 3-51 appendix 3.5 list of registers fig. 3.5.3 structure of i 2 c data shift register fig. 3.5.4 structure of i 2 c address register b 7b 6b 5b 4b3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? i 2 c d a t a s h i f t r e g i s t e r i 2 c data shift register (s0) [address : 12 16 ] t h i s r e g i s t e r i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a o r w r i t e t r a n s m i t d a t a . note: secure 8 machine cycles from clearing mst bit to 0 (slave mode) until writing data to i 2 c data shift register. if executing the read-modify-write instruction(seb, clb etc.) for this register during transfer, data may become a value not intended. b7 b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t reset rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 i 2 c a d d r e s s r e g i s t e r ( s 0 d ) [ a d d r e s s : 1 3 ] read / write bit (rwb) 0 : write bit 1 : read bit 0 0 0 n o t e : i f t h e r e a d - m o d i f y - w r i t e i n s t r u c t i o n ( s e b , c l b , e t c . ) i s e x e c u t e d f o r t h i s r e g i s t e r a t d e t e c t i n g t h e s t o p c o n d i t i o n , d a t a m a y b e c o m e a v a l u e n o t t o i n t e n d . i 2 c a d d r e s s r e g i s t e r 1 6 s l a v e a d d r e s s ( s a d 0 , s a d 1 , s a d 2 , s a d 3 , s a d 4 , s a d 5 , s a d 6 ) these bits are compared with the address data transmitted from the master.
3886 group user s manual 3-52 appendix 3.5 list of registers fig. 3.5.5 structure of i 2 c status register b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 1 0 0 i 2 c s t a t u s r e g i s t e r ( s 1 ) [ a d d r e s s : 1 4 1 6 ] i 2 c s t a t u s r e g i s t e r 0 ? l a s t r e c e i v e b i t ( l r b ) b u s b u s y f l a g ( b b ) a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) 0 : not detected 1 : detected ( note1 ) communication mode specification bits (trx, mst) 00 : slave receive mode 01 : slave transmit mode 10 : master receive mode 11 : master transmit mode 0 0 0 : last bit = 0 1 : last bit = 1 ( note1 ) g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) 0 : no general call detected 1 : general call detected( note1, 2 ) s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) 0 : address disagreement 1 : address agreement ( note1, 2 ) ? ? ? ? scl pin low hold bit (pin) 0 : scl pin low hold 1 : scl pin low release n o t e s 1 : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n o t b e w r i t t e n . 2 : t h e s e b i t s c a n b e d e t e c t e d w h e n d a t a f o r m a t s e l e c t i o n b i t ( a l s ) o f i c c o n t r o l r e g i s t e r i s 0 . 3 : d o n o t e x e c u t e t h e r e a d - m o d i f y - w r i t e i n s t r u c t i o n ( s e b , c l b ) f o r t h i s r e g i s t e r b e c a u s e a l l b i t s o f t h i s r e g i s t e r a r e c h a n g e d b y h a r d w a r e . : 1 c a n b e w r i t t e n t o t h i s b i t , b u t 0 c a n n o t b e w r i t t e n b y p r o g r a m . 2 0 : bus free 1 : bus busy ? ?
3886 group user s manual 3-53 appendix 3.5 list of registers fig. 3.5.6 structure of i 2 c control register i 2 c c o n t r o l r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 i 2 c control register (s1d) [address :15 16 ] b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c e i v e b i t s ) ( b c 0 , b c 1 , b c 2 ) 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 b 2 b 1 b 0 i 2 c - b u s i n t e r f a c e e n a b l e b i t ( e s 0 ) 0 : disabled 1 : enabled d a t a f o r m a t s e l e c t i o n b i t ( a l s ) 0 : addressing format 1 : free data format a d d r e s s i n g f o r m a t s e l e c t i o n b i t ( 1 0 b i t s a d ) 0 : 7-bit addressing format 1 : 10-bit addressing format s y s t e m c l o c k s t o p s e l e c t i o n b i t ( c l k s t p ) i 2 c-bus interface pin input level selection bit (tiss) 0 : s y s t e m c l o c k s t o p w h e n e x e c u t i n g w i t o r s t p i n s t r u c t i o n 1 : n o t s y s t e m c l o c k s t o p w h e n e x e c u t i n g w i t i n s t r u c t i o n ( d o n o t u s e t h e s t p i n s t r u c t i o n . ) 0 : cmos input 1 : smbus input notes : when the read-modify-write instruction is executed for this register at detecting the start condition or at completing the byte transfer, data may become a value not intended.
3886 group user s manual 3-54 appendix 3.5 list of registers fig. 3.5.7 structure of i 2 c clock control register table 3.5.1 set value of i 2 c clock control register and scl frequency scl frequency (at = 4 mhz, unit : khz) (note 3) setting value of ccr4 ccr0 standard clck mode setting disabled setting disabled setting disabled high-speed clock mode ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 setting disabled setting disabled setting disabled 34.5 33.3 32.3 100 83.3 333 250 400 (note 2) 166 (note 1) (note 1) 500/ccr value 1000/ccr value 17.2 16.6 16.1 notes 1: each value of s cl frequency exceeds the limit at = 4 mhz or more. when using these setting value, use of 4 mhz or less. 2: the data formula of s cl frequency is described below: /(8 ? ccr value) standard clock mode /(4 ? ccr value) high-speed clock mode (ccr value 5) /(2 ? ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as ccr value regardless of frequency. set 100 khz (max.) in the standard clock mode and 400 khz (max.) in the high-speed clock mode to the s cl frequency by setting the s cl frequency control bits ccr4 to ccr0. 3: duty of s cl clock output is 50 %. the duty becomes 35 to 45 % only when the high-speed clock mode is selected and ccr value = 5 (400 khz, at = 4 mhz). h duration of the clock fluctuates from 4 to +2 machine cycles in the standard clock mode, and fluctuates from 2 to +2 machine cycles in the high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because l duration is extended instead of h duration reduction. these are value when s cl clock synchronization by the synchronous function is not performed. ccr value is the decimal notation value of the s cl frequency control bits ccr4 to ccr0. b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 2 3 4 5 6 7 name i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) [ a d d r e s s : 1 6 1 6 ] i 2 c c l o c k c o n t r o l r e g i s t e r 0 0 0 1 scl frequency control bits (ccr0, ccr1, ccr2, ccr3, ccr4) 0 : standard clock mode 1 : high-speed clock mode scl mode specification bit (fast mode) ack bit (ack bit) ack clock bit (ack) 0 : ack is returned 1 : ack is not returned 0 : no ack clock 1 : ack clock refer to table 3.5.1 0
3886 group user s manual 3-55 appendix 3.5 list of registers fig. 3.5.9 structure of transmit/receive buffer register fig. 3.5.8 structure of i 2 c start/stop condition control register b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 2 3 4 5 6 7 name 0 i 2 c start/stop condition control register (s2d) [address : 17 16 ] i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r 0 ? 1 s t a r t / s t o p c o n d i t i o n s e t b i t ( s s c 0 , s s c 1 , s s c 2 , s s c 3 , s s c 4 )( n o t e ) 0 : falling edge active 1 : rising edge active s c l / s d a i n t e r r u p t p i n p o l a r i t y s e l e c t i o n b i t ( s i p ) s cl /s da interrupt pin selection bit (sis) s c l r e l e a s e t i m e = ( s ) ? ( s s c + 1 ) s e t u p t i m e = ( s ) ? ( s s c + 1 ) / 2 h o l d t i m e = ( s ) ? ( s s c + 1 ) / 2 0 : s da valid 1 : s cl valid s t a r t / s t o p c o n d i t i o n g e n e r a t i n g s e l e c t i o n b i t ( s t s p s e l ) 0 0 : setup/hold time short mode 1 : setup/hold time long mode n o t e : d o n o t s e t 0 0 0 0 0 2 o r a n o d d n u m b e r t o t h e s t a r t / s t o p c o n d i t i o n s e t b i t ( s s c 4 t o s s c 0 ) . t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t reset rw 0 1 2 3 4 5 6 7 name ? ? ? ? ? ? ? ? transmit/receive buffer register (tb/rb) [address : 18 16 ] the transmission data is written to or the receive data is read out from this buffer register. at writing: a data is written to the transmit buffer register. at reading: the contents of the receive buffer register are read out. note: the contents of transmit buffer register cannot be read out. the data cannot be written to the receive buffer register.
3886 group user s manual 3-56 appendix 3.5 list of registers fig. 3.5.10 structure of serial i/o1 status register fig. 3.5.11 structure of serial i/o1 control register s e r i a l i / o 1 s t a t u s r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 1 s e r i a l i / o 1 s t a t u s r e g i s t e r ( s i o 1 s t s ) [ a d d r e s s : 1 9 1 6 ] nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 1 . ? ? ? ? ? ? ? ? t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : (oe) u (pe) u (fe) = 0 1 : (oe) u (pe) u (fe) = 1 o v e r r u n e r r o r f l a g ( o e ) 0 : buffer full 1 : buffer empty r e c e i v e b u f f e r f u l l f l a g ( r b f ) t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) p a r i t y e r r o r f l a g ( p e ) framing error flag (fe) s u m m i n g e r r o r f l a g ( s e ) 0 : buffer empty 1 : buffer full 0 : transmit shift in progress 1 : transmit shift completed 0 : no error 1 : overrun error 0 : no error 1 : parity error 0 : no error 1 : framing error s e r i a l i / o 1 c o n t r o l r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) [ a d d r e s s : 1 a 1 6 ] 0 : f ( x i n ) ( f ( x c in ) i n l o w s p e e d m o d e ) 1 : f ( x i n ) / 4 ( f ( x c i n ) / 4 i n l o w s p e e d m o d e ) b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) t r a n s m i t e n a b l e b i t ( t e ) r e c e i v e e n a b l e b i t ( r e ) s e r i a l i / o 1 e n a b l e b i t ( s i o e ) s r d y 1 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 4 7 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 4 7 p i n o p e r a t e s a s s r d y 1 o u t p u t p i n 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) i n c l o c k s y n c h r o n o u s s e r i a l i / o 0 : b r g o u t p u t d e v i d e d b y 4 1 : e x t e r n a l c l o c k i n p u t i n u a r t 0 : b r g o u t p u t d e v i d e d b y 1 6 1 : e x t e r n a l c l o c k i n p u t d e v i d e d b y 1 6 s e r i a l i / o 1 m o d e s e l e c t i o n b i t ( s i o m ) 0 : c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o 1 : c l o c k s y n c h r o n o u s s e r i a l i / o 0 : s e r i a l i / o 1 d i s a b l e d ( p i n s p 4 4 t o p 4 7 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o 1 e n a b l e d ( p i n s p 4 4 t o p 4 7 o p e r a t e a s s e r i a l i / o p i n s )
3886 group user s manual 3-57 appendix 3.5 list of registers fig. 3.5.13 structure of baud rate generator fig. 3.5.12 structure of uart control register b7 b 6b 5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 1 uart control register (uartcon) [address : 1b 16 ] n o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . t h e s e a r e w r i t e d i s a b l e d b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 1 . ? ? ? u a r t c o n t r o l r e g i s t e r c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) p a r i t y e n a b l e b i t ( p a r e ) s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) parity selection bit (pars) i n o u t p u t m o d e 0 : c m o s o u t p u t 1 : n - c h a n n e l o p e n - d r a i n o u t p u t 0 : 8 bits 1 : 7 bits 0 : parity checking disabled 1 : parity checking enabled 0 : 1 stop bit 1 : 2 stop bits 0 : even parity 1 : odd parity p 4 5 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 1 1 0 baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? b a u d r a t e g e n e r a t o r ( b r g ) [ a d d r e s s : 1 c 1 6 ] set a count value of baud rate generator.
3886 group user s manual 3-58 appendix 3.5 list of registers fig. 3.5.14 structure of serial i/o2 control register fig. 3.5.15 structure of watchdog timer control register b7 b 6b 5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 serial i/o2 control register (sio2con) [address : 1d 16 ] serial i/o2 control register 0 0 0 0 : f ( x i n ) / 8 0 0 1 : f ( x i n ) / 1 6 0 1 0 : f ( x i n ) / 3 2 0 1 1 : f ( x i n ) / 6 4 1 1 0 : f ( x i n ) / 1 2 8 1 1 1 : f ( x i n ) / 2 5 6 internal synchronous clock selection bits b 2 b 1 b 0 s e r i a l i / o 2 p o r t s e l e c t i o n b i t 0 : i / o p o r t ( p 7 1 , p 7 2 ) 1 : s o u t 2 , s c l k 2 s i g n a l o u t p u t 0 s r d y 2 o u t p u t e n a b l e b i t 0 : i / o p o r t ( p 7 3 ) 1 : s r d y 2 s i g n a l o u t p u t t r a n s f e r d i r e c t i o n s e l e c t i o n b i t0 : l s b f i r s t 1 : m s b f i r s t serial i/o2 synchronous clock selection bit 0: external clock 1: internal clock c o m p a r a t o r r e f e r e n c e i n p u t s e l e c t i o n b i t 0 : p 0 0 / p 3 r e f i n p u t 1 : r e f e r e n c e i n p u t f i x e d 0 0 watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 1 1 1 1 1 1 0 0 w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n ) [ a d d r e s s : 1 e 1 6 ] w a t c h d o g t i m e r h ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t s ) stp instruction disable bit 0 : stp instruction enabled 1 : stp instruction disabled w a t c h d o g t i m e r h c o u n t s o u r c e s e l e c t i o n b i t 0 : watchdog timer l underflow 1 : f(x in )/16 or f(x cin )/16 ? ? ? ? ? ?
3886 group user s manual 3-59 appendix 3.5 list of registers fig. 3.5.16 structure of serial i/o2 register fig. 3.5.17 structure of prescaler 12, prescaler x, prescaler y serial i/o2 register b 7b 6b 5b 4b3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 name ? ? ? ? ? ? ? ? serial i/o2 register (sio2) [address : 1f 16 ] s e r i a l i / o 2 r e g i s t e r i s t h e s h i f t r e g i s t e r f o r s e r i a l t r a n s f e r . a t t r a n s m i t : t r a n s m i t d a t a i s s e t . a t r e c e i v e : r e c e i v e d a t a i s s e t . prescaler 12, prescaler x, prescaler y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 1 1 prescaler 12 (pre12) [address : 20 16 ] prescaler x (prex) [address : 24 16 ] prescaler y (prey) [address : 26 16 ] set a count value of each prescaler. the value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time. when this register is read out, the count value of the corres- ponding prescaler is read out.
3886 group user s manual 3-60 appendix 3.5 list of registers fig. 3.5.18 structure of timer 1 fig. 3.5.19 structure of timer 2, timer x, timer y timer 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 0 0 0 0 0 0 0 timer 1 (t1) [address : 21 16 ] set a count value of timer 1. the value set in this register is written to both timer 1 and timer 1 latch at the same time. when this register is read out, the timer 1 s count value is read out. timer 2, timer x, timer y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 1 1 timer 2 (t2) [address : 22 16 ] timer x (tx) [address : 25 16 ] timer y (ty) [address : 27 16 ] set a count value of each timer. the value set in this register is written to both each timer and each timer latch at the same time. when this register is read out, each timer s count value is read out.
3886 group user s manual 3-61 appendix 3.5 list of registers fig. 3.5.20 structure of timer xy mode register timer x /timer y operation modes timer mode pulse output mode event counter mode pulse width measurement mode cntr 0 / cntr 1 active edge selection bit (bits 2, 6 of address 23 16 ) contents 0 cntr 0 / cntr 1 interrupt request occurrence: falling edge ; no influence to timer count 1 cntr 0 / cntr 1 interrupt request occurrence: rising edge ; no influence to timer count 0 pulse output start: beginning at h level cntr 0 / cntr 1 interrupt request occurrence: falling edge 1 pulse output start: beginning at l level cntr 0 / cntr 1 interrupt request occurrence: rising edge 0 timer x / timer y: rising edge count cntr 0 / cntr 1 interrupt request occurrence: falling edge 1 timer x / timer y: falling edge count cntr 0 / cntr 1 interrupt request occurrence: rising edge 0 timer x / timer y: h level width measurement cntr 0 / cntr 1 interrupt request occurrence: falling edge 1 timer x / timer y: l level width measurement cntr 0 / cntr 1 interrupt request occurrence: rising edge table 3.5.2 cntr 0 /cntr 1 active edge selection bit function b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 3 4 5 6 7 name 0 0 0 0 timer xy mode register (tm) [address : 23 16 ] timer xy mode register 0 0 0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b1 b0 1 0 timer x operating mode bits cntr 0 active edge selection bit the function depends on the operating mode of timer x. (refer to table 3.5.2) timer x count stop bit 0 : count start 1 : count stop timer y operating mode bits 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b5 b4 the function depends on the operating mode of timer y. (refer to table 3.5.2) 0 : count start 1 : count stop cntr 1 active edge selection bit timer y count stop bit
3886 group user s manual 3-62 appendix 3.5 list of registers fig. 3.5.21 structure of data bus buffer register fig. 3.5.22 structure of data bus buffer status register d a t a b u s b u f f e r r e g i s t e r i b 7b 6b5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 name ? ? ? ? ? ? ? ? d a t a b u s b u f f e r r e g i s t e r i ( d b b i ) ( i = 0 , 1 ) [ a d d r e s s : 2 8 1 6 / 2 b 1 6 ] b u f f e r r e g i s t e r t o w r i t e o u t p u t d a t a a n d r e a d i n p u t d a t a . a t w r i t e : d a t a i s w r i t t e n t o o u t p u t d a t a b u f f e r r e g i s t e r . a t r e a d : t h e c o n t e n t s o f i n p u t d a t a b u f f e r r e g i s t e r a r e r e a d o u t . n o t e : o u t p u t d a t a b u s b u f f e r a n d i n p u t d a t a b u s b u f f e r a r e s s i g n e d t o t h e s a m e a d d r e s s . t h e c o n t e n t s o f o u t p u t d a t a b u s b u f f e r r e g i s t e r c a n n o t b e r e a d o u t . w r i t i n g t o i n p u t d a t a b u s b u f f e r r e g i s t e r i s d i s a b l e d . 7 data bus buffer status register i b7 b6 b5 b4 b3 b2 b1 b0 b function a t reset rw 0 1 2 3 4 name 0 0 0 0 0 o u t p u t b u f f e r f u l l f l a g i input buffer full flag i 0 : buffer empty 1 : buffer full u s e r d e f i n a b l e f l a g s ( t h i s f l a g c a n b e d e f i n e d b y u s e r f r e e l y . ) a 0 i f l a g u s e r d e f i n a b l e f l a g s ( t h i s f l a g c a n b e d e f i n e d b y u s e r f r e e l y . ) 0 : buffer empty 1 : buffer full this flag indicates the condition of a 0i status when the ibf i flag is set. data bus buffer status register i (dbbstsi) (i=0, 1) [address 29 16 /2c 16 ] 50 60 0 ? ? ?
3886 group user s manual 3-63 appendix 3.5 list of registers fig. 3.5.23 structure of data bus buffer control register fig. 3.5.24 structure of comparator data register 0 : p4 2 functions as port i/o pin. 1 : p4 2 functions as obf 00 output pin. d a t a b u s b u f f e r c o n t r o l r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 d a t a b u s b u f f e r c o n t r o l r e g i s t e r ( d b b c o n ) [ a d d r e s s 2 a 1 6 ] fix this bit to 0 . d a t a b u s b u f f e r e n a b l e b i t d a t a b u s b u f f e r f u n c t i o n s e l e c t i o n b i t 0 : p5 0 p5 3 , p8 i/o port 1 : data bus buffer enabled o b f 1 0 o u t p u t e n a b l e b i t input level selection bit o b f 0 o u t p u t s e l e c t i o n b i t obf 00 output enable bit o b f 0 1 o u t p u t e n a b l e b i t 0 : single data bus buffer mode (p4 7 functions as i/o port.) 1 : double data bus buffer mode (p4 7 functions as s 1 input.) 0 : obf 00 valid 1 : obf 01 valid 0 : p4 3 functions as port i/o pin. 1 : p4 3 functions as obf 01 output pin. 0 : p4 6 functions as port i/o pin. 1 : p4 6 functions as obf 10 output pin. 0 : cmos level input 1 : ttl level input comparator data register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name ? ? ? ? ? ? ? ? comparator data register (cmpd) [address : 2d 16 ] at writing: the voltage comparison is immediately performed by writing operation. at reading: the comparison result is read out.
3886 group user s manual 3-64 appendix 3.5 list of registers fig. 3.5.25 structure of port control register 1 fig. 3.5.26 structure of port control register 2 p o r t c o n t r o l r e g i s t e r 1 b 7b 6b 5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 p o r t c o n t r o l r e g i s t e r 1 ( p c t l 1 ) [ a d d r e s s 2 e 1 6 ] p w m 1 e n a b l e b i t p0 0 p0 3 output structure selection bit 0: pwm 0 output disabled 1: pwm 0 output enabled p 1 4 p 1 7 o u t p u t s t r u c t u r e s e l e c t i o n b i t 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n p 0 4 p 0 7 o u t p u t s t r u c t u r e s e l e c t i o n b i t p 1 0 p 1 3 o u t p u t s t r u c t u r e s e l e c t i o n b i t p 3 0 p 3 3 p u l l - u p c o n t r o l b i t p3 4 p3 7 pull-up control bit p w m 0 e n a b l e b i t 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n 0 : n o p u l l - u p 1 : p u l l - u p 0 : n o p u l l - u p 1 : p u l l - u p 0 : p w m 1 o u t p u t d i s a b l e d 1 : p w m 1 o u t p u t e n a b l e d p o r t c o n t r o l r e g i s t e r 2 b7 b6 b5 b4 b3 b2 b1 b0 b function a t reset rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 port control register 2 (pctl2) [address 2f 16 ] p o r t o u t p u t p 4 2 / p 4 3 c l e a r f u n c t i o n s e l e c t i o n b i t p4 input level selection bit (p4 2 p4 6 ) 0 : a u t o m a t i c s e t 0 1 1 6 t o t i m e r 1 a n d f f 1 6 t o p r e s c a l e r 1 2 1 : n o a u t o m a t i c s e t p8 function selection bit 0 : c m o s l e v e l i n p u t 1 : t t l l e v e l i n p u t p 7 i n p u t l e v e l s e l e c t i o n b i t ( p 7 0 p 7 5 ) p4 output structure selection bit (p4 2 , p4 3 , p4 4 , p4 6 ) i n t 2 , i n t 3 , i n t 4 i n t e r r u p t s w i t c h b i t timer y count source selection bit o s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r s t p i n s t r u c t i o n r e l e a s e d b i t 0: cmos level input 1: ttl level input 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n 0 : p o r t p 8 / p o r t p 8 d i r e c t i o n r e g i s t e r 1 : p o r t p 4 i n p u t r e g i s t e r / p o r t p 7 i n p u t r e g i s t e r 0 : i n t 2 0 , i n t 3 0 , i n t 4 0 i n t e r r u p t 1 : i n t 2 1 , i n t 3 1 , i n t 4 1 i n t e r r u p t 0 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) 1 : f ( x c i n ) 0 : o n l y s o f t w a r e c l e a r 1 : s o f t w a r e c l e a r a n d o u t p u t d a t a b u s b u f f e r 0 r e a d i n g ( s y s t e m b u s s i d e )
3886 group user s manual 3-65 appendix 3.5 list of registers fig. 3.5.27 structure of pwm0h register fig. 3.5.28 structure of pwm0l register pwm0h register b 7b 6b5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? p w m 0 h r e g i s t e r ( p w m 0 h ) [ a d d r e s s : 3 0 1 6 ] t h e h i g h - o r d e r 8 b i t s o f t h e p w m 0 h o u t p u t d a t a a r e s e t . a t w r i t i n g : a w r i t t e n d a t a i s t r a n s f e r r e d t o p w m 0 l a t c h a t e v e r y s u b - p e r i o d ( 6 4 s ) . ( f ( x i n ) = 8 m h z ) a t r e a d i n g : t h e c o n t e n t s o f t h e p w m 0 h r e g i s t e r a r e r e a d o u t . pwm0l register b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 6 7 ? ? ? p w m 0 l r e g i s t e r ( p w m 0 l ) [ a d d r e s s : 3 1 1 6 ] t h e l o w - o r d e r 6 b i t s o f t h e p w m 0 l o u t p u t d a t a a r e s e t . a t w r i t i n g : a w r i t t e n d a t a i s t r a n s f e r r e d t o p w m 0 l a t c h a t e v e r y r e p e t i t i v e p e r i o d ( 4 0 9 6 s ) . ( f ( x i n ) = 8 m h z ) a t r e a d i n g : t h e l o w - o r d e r 6 b i t s o f p w m 0 l a t c h a r e r e a d o u t . ? ? ? ? ? ? 5 ? n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . t h e c o m p l e t i o n o f t r a n s f e r t o t h e p w m 0 l a t c h i s i n d i c a t e d . 0 : t r a n s f e r c o m p l e t e d . 1 : n o t t r a n s f e r r e d . a t w r i t i n g : t h i s b i t i s s e t t o 1 .
3886 group user s manual 3-66 appendix 3.5 list of registers fig. 3.5.29 structure of pwm1h register fig. 3.5.30 structure of pwm1l register pwm1h register b 7b 6b5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? p w m 1 h r e g i s t e r ( p w m 1 h ) [ a d d r e s s : 3 2 1 6 ] t h e h i g h - o r d e r 8 b i t s o f t h e p w m 1 h o u t p u t d a t a a r e s e t . a t w r i t i n g : a w r i t t e n d a t a i s t r a n s f e r r e d t o p w m 1 l a t c h a t e v e r y s u b - p e r i o d ( 6 4 s ) . ( f ( x i n ) = 8 m h z ) a t r e a d i n g : t h e c o n t e n t s o f t h e p w m 1 h r e g i s t e r a r e r e a d o u t . pwm1l register b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 6 7 ? ? ? p w m 1 l r e g i s t e r ( p w m 1 l ) [ a d d r e s s : 3 3 1 6 ] the low-order 6 bits of the pwm1l output data are set. at writing: a written data is transferred to pwm1 latch at every repetitive period (4096 s). (f(x in ) = 8 mhz) at reading: the low-order 6 bits of pwm1 latch are read out. ? ? ? ? ? ? 5 ? nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0 . the completion of transfer to the pwm1 latch is indicated. 0: transfer completed. 1: not transferred. at writing: this bit is set to 1 .
3886 group user s manual 3-67 appendix 3.5 list of registers fig. 3.5.31 structure of ad/da control register fig. 3.5.32 structure of ad conversion register 1 a-d conversion register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 ) [ a d d r e s s : 3 5 1 6 ] the read-only register in which the a-d conversion s results are stored. ? ? ? ? ? ? ? ? < 8-bit read> b7 b8 b7 b6 b 5b 4b 3 b 0 b 2 b9 < 10-bit read> b7 b6 b5 b4 b 3b 2b 1 b 0 b 0 b7 ad/da control register b7 b6 b5 b4 b3 b2 b1 b0 ad/da control register (adcon: address 34 16 ) b 0 1 2 name 0 functions at reset r w 0 0 1 analog input pin selection bits b2 b1 b0 0 0 0: p6 0 /an 0 0 0 1: p6 1 /an 1 0 1 0: p6 2 /an 2 0 1 1: p6 3 /an 3 1 0 0: p6 4 /an 4 1 0 1: p6 5 /an 5 1 1 0: p6 6 /an 6 1 1 1: p6 7 /an 7 3 0 pwm 0 output pin selection bit 0: p5 6 /pwm 01 1: p3 0 /pwm 00 ad conversion completion bit 0: conversion in progress 1: conversion completed 4 0 5 0 da 1 output enable bit 0: da 1 output disabled 1: da 1 output enabled 0 da 2 output enable bit 0: da 2 output disabled 1: da 2 output enabled 6 7 pwm 1 output pin selection bit 0: p5 7 /pwm 11 1: p3 1 /pwm 10
3886 group user s manual 3-68 appendix 3.5 list of registers fig. 3.5.33 structure of d-ai conversion register fig. 3.5.34 structure of a-d convesion register 2 d-ai conversion register b7 b6 b5 b4 b3 b2 b1 b0 d-ai conversion register (dai) (i = 1, 2) [address: 36 16 , 37 16 ] b 0 0 0 0 0 0 0 0 at reset r w 1 2 3 4 5 6 7 functions this is d-a output value stored bits. this is write exclusive register. 0 0 0 0 0 0 0 0 a - d c o n v e r s i o n r e g i s t e r 2 b 7b 6b5b 4b 3b 2b 1b 0 b function a t reset rw 0 1 2 3 4 5 6 7 name ? ? ? ? ? ? ? ? t h e r e a d - o n l y r e g i s t e r i n w h i c h t h e a - d c o n v e r s i o n s r e s u l t s a r e s t o r e d . ? ? ? ? ? ? ? < 10-bit read> b7 b9 b0 b 8 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0 . a - d c o n v e r s i o n r e g i s t e r 2 ( a d 2 ) [ a d d r e s s : 3 8 ] 16 c o n v e r s i o n m o d e s e l e c t i o n b i t 0 : 1 0 - b i t a - d m o d e 1 : 8 - b i t a - d m o d e
3886 group user s manual 3-69 appendix 3.5 list of registers fig. 3.5.35 structure of interrupt source selection register fig. 3.5.36 structure of interrupt edge selection register i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r b 7b 6b5b 4b 3b 2b 1b 0 b f u n c t i o n a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t s o u r c e s e l e c t i o n b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 0 i n t e r r u p t 1 : i n p u t b u f f e r f u l l i n t e r r u p t int 2 /i 2 c interrupt source selection bit cntr 1 /key-on wake-up interrupt source selection bit 0 : i n t 1 i n t e r r u p t 1 : o u t p u t b u f f e r e m p t y i n t e r r u p t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t c n t r 0 / s c l , s d a i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : s e r i a l i / o 1 t r a n s m i t i n t e r r u p t 1 : s c l , s d a i n t e r r u p t 0 : c n t r 0 i n t e r r u p t 1 : s c l , s d a i n t e r r u p t s e r i a l i / o 2 / i 2 c i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : serial i/o2 interrupt 1 : i 2 c interrupt 0 : int 2 interrupt 1 : i 2 c interrupt 0 : c n t r 1 i n t e r r u p t 1 : k e y - o n w a k e - u p i n t e r r u p t a d c o n v e r t e r / k e y - o n w a k e - u p i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : a - d c o n v e r t e r i n t e r r u p t 1 : k e y - o n w a k e - u p i n t e r r u p t ? 1 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 2 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ? 3 : d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . interrupt source selection register [intsel: address 0039 16 ] ? 1 ? 2 ? 2 ? 3 ? 3 ? 1 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r b 7b 6b5b 4b 3b 2b 1b 0 b function a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt edge selection register (intedge) [address : 3a 16 ] n o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . t h e s e a r e w r i t e d i s a b l e d b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active i n t 3 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 2 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active ? ? ? n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . i n t 4 i n t e r r u p t e d g e s e l e c t i o n b i t 0 : falling edge active 1 : rising edge active
3886 group user s manual 3-70 appendix 3.5 list of registers fig. 3.5.37 structure of cpu mode register cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 cpu mode register (cpum: address 3b 16 ) 00 : single-chip mode 01 : memory expansion mode (note) 10 : microprocessor mode (note) 11 : not available b 0 1 1 2 3 4 5 6 7 name 0 functions at reset r w 0 : 0 page 1 : 1 page 0 1 0 0: oscillating 1: stopped 0 1 0 processor mode bits stack page selection bit port xc switch bit fix this bit to 1 . main clock (x in - x out ) stop bit main clock division ratio selection bits * : the initial value of bit 1 depends on the cnvss level. note: this mode is not available for m3886 9m8a/mca/mfa or the flash memory version. b1 b0 b7 b6 0 0: =f(x in )/2 (high-speed mode) 0 1: =f(x in )/8 (middle-speed mode) 1 0: =f(x cin )/2 (low-speed mode) 1 1: not available 0: i/o port function (oscillation stopped) 1: x cin -x cout oscillation function *
3886 group user s manual 3-71 appendix 3.5 list of registers fig. 3.5.39 structure of interrupt request register 2 fig. 3.5.38 structure of interrupt request register 1 interrupt request register 1 b 7b 6b 5b 4b3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 1 (ireq1) [address : 3c 16 ] int 0 /input buffer full interrupt request bit int 1 /output buffer empty interrupt request bit 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d timer y interrupt request bit timer 1 interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d serial i/o1 receive interrupt request bit serial i/o1 transmit/s cl , s da interrupt request bit 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ? ? ? ? ? ? ? timer 2 interrupt request bit 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ? interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b f u n c t i o n a t reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] n o t h i n g i s a l l o c a t e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . ? cntr 0 /s cl , s da interrupt request bit cntr 1 /key-on wake-up interrupt request bit 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d int 4 interrupt request bit ad converter/key-on wake-up interrupt request bit ? : these bits can be cleared to 0 by program, but cannot be set to 1 . 0 : no interrupt request issued 1 : interrupt request issued serial i/o2/i 2 c interrupt request bit int 2 /i 2 c interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d int 3 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ? ? ? ? ? ? ?
3886 group user s manual 3-72 appendix 3.5 list of registers fig. 3.5.40 structure of interrupt control register 1 fig. 3.5.41 structure of interrupt control register 2 i n t e r r u p t c o n t r o l r e g i s t e r 1 b 7b 6b 5b 4b 3b 2b 1b 0 b function a t r e s e t rw 0 1 2 3 4 5 6 7 n a m e 0 0 0 0 0 0 0 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s : 3 e 1 6 ] i n t 0 / i n p u t b u f f e r f u l l i n t e r r u p t e n a b l e b i t i n t 1 / o u t p u t b u f f e r e m p t y i n t e r r u p t e n a b l e b i t 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d t i m e r y i n t e r r u p t e n a b l e b i t t i m e r 1 i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t / s c l , s d a i n t e r r u p t e n a b l e b i t timer x interrupt enable bit 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : interrupt disabled 1 : interrupt enabled 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d t i m e r 2 i n t e r r u p t e n a b l e b i t 0 : interrupt disabled 1 : interrupt enabled i n t e r r u p t c o n t r o l r e g i s t e r 2 b 7b 6b 5b 4b 3b 2b 1b 0 b f u n c t i o n a t r e s e t rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] f i x t h i s b i t t o 0 . c n t r 0 / s c l , s d a i n t e r r u p t e n a b l e b i t cntr 1 /key-on wake-up interrupt enable bit 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d int 4 interrupt enable bit a d c o n v e r t e r / k e y - o n w a k e - u p i n t e r r u p t e n a b l e b i t serial i/o2/i 2 c interrupt enable bit i n t 2 / i 2 c i n t e r r u p t e n a b l e b i t i n t 3 i n t e r r u p t e n a b l e b i t 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : interrupt disabled 1 : interrupt enabled 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0
3886 group user s manual 3-73 appendix 3.5 list of registers fig. 3.5.42 structure of flash memory control register flash memory control register b7 b6 b5 b4 b3 b2 b1 b0 flash memory control register (fcon : address ffe 16 ) b 0 00 1 2 4 name 0 functions at reset r w 0 0 0 0 erase/program busy flag fix this bit to 0 . erase/program area select bits cpu reprogramming mode monitor flag 0 : cpu reprogramming mode is invalid. (normal operation mode) 1 : when applying 0 v to cnv ss /v pp pin, cpu reprogramming mode is invalid. when applying v pp h to cnv ss /v pp pin, cpu reprogramming mode is valid. 0 : erase and program are completed or have not been executed. 1 : erase/program is being executed. 0 : cpu reprogramming mode is invalid 1 : cpu reprogramming mode is valid 5 0 6 7 0 fix this bit to 0 . 0 cpu reprogramming mode select bit (note) nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are 0 . note: bit 0 can be reprogrammed only when 0 v is applied to the cnv ss /v pp pin. 3 b5 b4 0 0: address 1000 16 to ffff 16 (total 60kbytes) 0 1: address 1000 16 to 7fff 16 (total 28kbytes) 1 0: address 8000 16 to ffff 16 (total 32kbytes) 1 1: not available
3886 group user s manual 3-74 appendix 3.5 list of registers fig. 3.5.43 structure of flash command register flash command register b7 b6 b5 b4 b3 b2 b1 b0 flash command register (fcmd: address fff 16 ) b 0 0 at reset r w 1 2 3 4 5 6 7 functions writing of software command read command program command program verify command erase command erase verify command reset command 00 16 40 16 c0 16 20 16 + 20 16 a0 16 ff 16 + ff 16 note: the flash command register is a write-only register. 0 0 0 0 0 0 0
3886 group user? manual appendix 3-75 3.6 package outline 3.6 package outline lqfp80-p-1212-0.5 weight(g) 0.47 jedec code eiaj package code lead material cu alloy 80p6q-a plastic 80pin 12 ? 12mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 0.9 m d 12.4 m e 12.4 10 0 0.1 1.0 0.7 0.5 0.3 14.2 14.0 13.8 14.2 14.0 13.8 0.5 12.1 12.0 11.9 12.1 12.0 11.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e a f e h d e h e d 1 20 21 40 41 60 61 80 y lp 0.45 0.6 0.25 0.75 0.08 x a3 m d l 2 b 2 m e e recommended mount pad b x m a 1 a 2 l 1 l detail f lp a3 c mmp weight(g) jedec code eiaj package code 80d0 glass seal 80pin qfn 25 40 80 65 41 64 24 1 1.2typ 0.6typ 0.8typ index 1.78typ 3.32max 0.8typ 1.2typ 0.8typ 0.5typ 12.0 0.15 15.6 0.2 21.0 0.2 18.4 0.15
3886 group user? manual 3-77 appendix 3.7 machine instructions addressing mode symbol function details imp imm a bit, a zp bit, zp opn#opn#opn#opn#opn# op n # 3-76 appendix 3886 group user? manual 3.7 machine instructions 75 35 16 4 4 6 2 2 2 6d 2d 0e 2c 4 4 6 4 3 3 3 3 7d 3d 1e 5 5 7 3 3 3 79 39 5 5 3 3 61 21 6 6 2 2 90 b0 f0 2 2 2 2 2 2 71 31 6 6 2 2 n n n m 7 v m 6 z z z z c c when t = 0, this instruction adds the contents m, c, and a; and stores the results in a and c. when t = 1, this instruction adds the contents of m(x), m and c; and stores the results in m(x) and c. when t=1, the contents of a re- main unchanged, but the contents of status flags are changed. m(x) represents the contents of memory where is indicated by x. when t = 0, this instruction transfers the con- tents of a and m to the alu which performs a bit-wise and operation and stores the result back in a. when t = 1, this instruction transfers the con- tents m(x) and m to the alu which performs a bit-wise and operation and stores the results back in m(x). when t = 1 the contents of a re- main unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. this instruction shifts the content of a or m by one bit to the left, with bit 0 always being set to 0 and bit 7 of a or m always being contained in c. this instruction tests the designated bit i of m or a and takes a branch if the bit is 0. the branch address is specified by a relative ad- dress. if the bit is 1, next instruction is executed. this instruction tests the designated bit i of the m or a and takes a branch if the bit is 1. the branch address is specified by a relative ad- dress. if the bit is 0, next instruction is executed. this instruction takes a branch to the ap- pointed address if c is 0. the branch address is specified by a relative address. if c is 1, the next instruction is executed. this instruction takes a branch to the ap- pointed address if c is 1. the branch address is specified by a relative address. if c is 0, the next instruction is executed. this instruction takes a branch to the ap- pointed address when z is 1. the branch address is specified by a relative address. if z is 0, the next instruction is executed. this instruction takes a bit-wise logical and of a and m contents; however, the contents of a and m are not modified. the contents of n, v, z are changed, but the contents of a, m remain unchanged. this instruction takes a branch to the ap- pointed address when n is 1. the branch address is specified by a relative address. if n is 0, the next instruction is executed. this instruction takes a branch to the ap- pointed address if z is 0. the branch address is specified by a relative address. if z is 1, the next instruction is executed. adc (note 1) (note 5) and (note 1) asl bbc (note 4) bbs (note 4) bcc (note 4) bcs (note 4) beq (note 4) bit bmi (note 4) bne (note 4) 7 0 c 0 29 2 2 0a 2 1 03 + 20i 17 + 20i 07 + 20i 06 5 2 25 3 2 3 65 3 2 69 2 2 4 4 2 2 13 + 20i 5 5 3 3 24 when t = 0 a a + m + c when t = 1 m(x) m(x) + m + c when t = 0 a a m when t = 1 m(x) m(x) m ai or mi = 0? ai or mi = 1? c = 0? c = 1? z = 1? a m n = 1? z = 0? v v v 2 3.7 machine instructions bit, a, r bit, zp, r 30 d0 2 2 2 2
3886 group user? manual 3-79 appendix 3.7 machine instructions addressing mode symbol function details imp imm a bit, a zp bit, zp opn#opn#opn#opn#opn# op n # 3-78 appendix 3886 group user? manual 3.7 machine instructions d5 d6 cd ec cc ce 50 70 2 2 2 2 n n n n n 0 4 6 4 4 4 6 3 3 3 3 dd de 5 7 3 3 d9 5 3 c1 6 2 d1 6 2 0 1 0 1 0 z z z z z 0 c c c 2 2 this instruction takes a branch to the ap- pointed address if n is 0. the branch address is specified by a relative address. if n is 1, the next instruction is executed. this instruction branches to the appointed ad- dress. the branch address is specified by a relative address. when the brk instruction is executed, the cpu pushes the current pc contents onto the stack. the badrs designated in the interrupt vector table is stored into the pc. this instruction takes a branch to the ap- pointed address if v is 0. the branch address is specified by a relative address. if v is 1, the next instruction is executed. this instruction takes a branch to the ap- pointed address when v is 1. the branch address is specified by a relative address. when v is 0, the next instruction is executed. this instruction clears the designated bit i of a or m. this instruction clears c. this instruction clears d. this instruction clears i. this instruction clears t. this instruction clears v. when t = 0, this instruction subtracts the con- tents of m from the contents of a. the result is not stored and the contents of a or m are not modified. when t = 1, the cmp subtracts the contents of m from the contents of m(x). the result is not stored and the contents of x, m, and a are not modified. m(x) represents the contents of memory where is indicated by x. this instruction takes the one? complement of the contents of m and stores the result in m. this instruction subtracts the contents of m from the contents of x. the result is not stored and the contents of x and m are not modified. this instruction subtracts the contents of m from the contents of y. the result is not stored and the contents of y and m are not modified. this instruction subtracts 1 from the contents of a or m. bpl (note 4) bra brk bvc (note 4) bvs (note 4) clb clc cld cli clt clv cmp (note 3) com cpx cpy dec n = 0? pc pc ?offset b 1 (pc) (pc) + 2 m(s) pc h s s ?1 m(s) pc l s s ?1 m(s) ps s s ?1 i 1 pc l ad l pc h ad h v = 0? v = 1? ai or mi 0 c 0 d 0 i 0 t 0 v 0 when t = 0 a ?m when t = 1 m(x) ?m __ m m x ?m y ?m a a ?1 or m m ?1 18 d8 58 12 b8 2 2 2 2 2 1 1 1 1 1 c9 e0 c0 2 2 2 2 2 2 1a 2 1 1b + 20i c5 44 e4 c4 c6 3 5 3 3 5 2 2 2 2 2 1f + 20i 21 52 00 7 1 10 80 2 4 2 2
3886 group user? manual 3-81 appendix 3.7 machine instructions addressing mode symbol function details imp imm a bit, a zp bit, zp opn#opn#opn#opn#opn# op n # 3-80 appendix 3886 group user? manual 3.7 machine instructions this instruction subtracts one from the current contents of x. this instruction subtracts one from the current contents of y. divides the 16-bit data in m(zz+(x)) (low-order byte) and m(zz+(x)+1) (high-order byte) by the contents of a. the quotient is stored in a and the one's complement of the remainder is pushed onto the stack. when t = 0, this instruction transfers the con- tents of the m and a to the alu which performs a bit-wise exclusive or, and stores the result in a. when t = 1, the contents of m(x) and m are transferred to the alu, which performs a bit- wise exclusive or and stores the results in m(x). the contents of a remain unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. this instruction adds one to the contents of a or m. this instruction adds one to the contents of x. this instruction adds one to the contents of y. this instruction jumps to the address desig- nated by the following three addressing modes: absolute indirect absolute zero page indirect absolute this instruction stores the contents of the pc in the stack, then jumps to the address desig- nated by the following addressing modes: absolute special page zero page indirect absolute when t = 0, this instruction transfers the con- tents of m to a. when t = 1, this instruction transfers the con- tents of m to (m(x)). the contents of a remain unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. this instruction loads the immediate value in m. this instruction loads the contents of m in x. this instruction loads the contents of m in y. dex dey div eor (note 1) inc inx iny jmp jsr lda (note 2) ldm ldx ldy x x ?1 y y ?1 a (m(zz + x + 1), m(zz + x )) / a m(s) one's comple- ment of remainder s s ?1 when t = 0 a a v m when t = 1 m(x) m(x) v m a a + 1 or m m + 1 x x + 1 y y + 1 if addressing mode is abs pc l ad l pc h ad h if addressing mode is ind pc l m (ad h , ad l ) pc h m (ad h , ad l + 1) if addressing mode is zp, ind pc l m(00, ad l ) pc h m(00, ad l + 1) m(s) pc h s s ?1 m(s) pc l s s ?1 after executing the above, if addressing mode is abs, pc l ad l pc h ad h if addressing mode is sp, pc l ad l pc h ff if addressing mode is zp, ind, pc l m(00, ad l ) pc h m(00, ad l + 1) when t = 0 a m when t = 1 m(x) m m nn x m y m 3a 21 1 1 1 1 2 2 2 2 ca 88 e8 c8 45 e6 3 5 2 2 49 22 e2 16 2 4d ee 4 6 3 3 5d fe 5 7 3 3 59 5 3 n n n n n n n n n z z z z z z z z z 41 6 2 51 6 2 b5 b4 4c 20 ad ae ac 6c a1 4 4 2 2 b6 4 2 3 6 4 4 4 3 3 3 3 3 bd bc 5 5 b9 be 5 5 3 3 3 3 53b2 02 4 7 2 2 62b162 22 5 2 a9 a2 a0 a5 3c a6 a4 3 4 3 3 2 3 2 2 2 2 2 2 2 2 55 f6 4 6 2 2
3886 group user? manual 3-83 appendix 3.7 machine instructions addressing mode symbol function details imp imm a bit, a zp bit, zp opn#opn#opn#opn#opn# op n # 3-82 appendix 3886 group user? manual 3.7 machine instructions 0 n n n n z z z z z c c c this instruction shifts either a or m one bit to the right such that bit 7 of the result always is set to 0, and the bit 0 is stored in c. multiplies accumulator with the memory speci- fied by the zero page x address mode and stores the high-order byte of the result on the stack and the low-order byte in a. this instruction adds one to the pc but does no otheroperation. when t = 0, this instruction transfers the con- tents of a and m to the alu which performs a bit-wise ?r? and stores the result in a. when t = 1, this instruction transfers the con- tents of m(x) and the m to the alu which performs a bit-wise or, and stores the result in m(x). the contents of a remain unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. this instruction pushes the contents of a to the memory location designated by s, and decrements the contents of s by one. this instruction pushes the contents of ps to the memory location designated by s and dec- rements the contents of s by one. this instruction increments s by one and stores the contents of the memory designated by s in a. this instruction increments s by one and stores the contents of the memory location designated by s in ps. this instruction shifts either a or m one bit left through c. c is stored in bit 0 and bit 7 is stored in c. this instruction shifts either a or m one bit right through c. c is stored in bit 7 and bit 0 is stored in c. this instruction rotates 4 bits of the m content to the right. this instruction increments s by one, and stores the contents of the memory location designated by s in ps. s is again incremented by one and stores the contents of the memory location designated by s in pc l . s is again incremented by one and stores the contents of memory location designated by s in pc h . this instruction increments s by one and stores the contents of the memory location designated by s in pc l . s is again incremented by one and the contents of the memory location is stored in pc h . pc is incremented by 1. lsr mul nop ora (note 1) pha php pla plp rol ror rrf rti rts m(s) a a ? m(zz + x) s s ?1 pc pc + 1 when t = 0 a a v m when t = 1 m(x) m(x) v m s s ?1 m(s) ps s s ?1 s s + 1 a m(s) s s + 1 ps m(s) s s + 1 ps m(s) s s + 1 pc l m(s) s s + 1 pc h m(s) s s + 1 pc l m(s) s s + 1 pc h m(s) (pc) (pc) + 1 7 0 c 7 0 7 0 c 7 0 0 c 4a 2 1 ea 2 1 09 2 2 46 05 5 3 2 2 2a 6a 26 66 82 48 08 68 28 40 60 3 3 4 4 6 6 1 1 1 1 1 1 2 2 1 1 5 5 8 2 2 2 56 62 15 6 15 4 2 2 2 4e 0d 6 4 3 3 5e 1d 7 5 3 3 19 53 01 6 2 11 6 2 36 76 2e 6e 6 6 2 2 6 6 3 3 3e 7e 7 7 3 3 (value saved in stack) (value saved in stack)
3886 group user? manual 3-85 appendix 3.7 machine instructions addressing mode symbol function details imp imm a bit, a zp bit, zp opn#opn#opn#opn#opn# op n # 3-84 appendix 3886 group user? manual 3.7 machine instructions n n n n n n z z z z z z when t = 0, this instruction subtracts the value of m and the complement of c from a, and stores the results in a and c. when t = 1, the instruction subtracts the con- tents of m and the complement of c from the contents of m(x), and stores the results in m(x) and c. a remain unchanged, but status flag are changed. m(x) represents the contents of memory where is indicated by x. this instruction sets the designated bit i of a or m. this instruction sets c. this instruction set d. this instruction set i. this instruction set t. this instruction stores the contents of a in m. the contents of a does not change. this instruction resets the oscillation control f/ f and the oscillation stops. reset or interrupt input is needed to wake up from this mode. this instruction stores the contents of x in m. the contents of x does not change. this instruction stores the contents of y in m. the contents of y does not change. this instruction stores the contents of a in x. the contents of a does not change. this instruction stores the contents of a in y. the contents of a does not change. this instruction tests whether the contents of m are ??or not and modifies the n and z. this instruction transfers the contents of s in x. this instruction stores the contents of x in a. this instruction stores the contents of x in s. this instruction stores the contents of y in a. the wit instruction stops the internal clock but not the oscillation of the oscillation circuit is not stopped. cpu starts its function after the timer x over flows (comes to the terminal count). all regis- ters or internal memory contents except timer x will not change during this mode. (of course needs vdd). sbc (note 1) (note 5) seb sec sed sei set sta stp stx sty tax tay tst tsx txa txs tya wit when t = 0 _ a a ?m ?c when t = 1 _ m(x) m(x) ?m ?c ai or mi 1 c 1 d 1 i 1 t 1 m a m x m y x a y a m = 0? x s a x s x a y 85 86 84 64 4 4 4 3 2 2 2 2 notes 1 : the number of cycles ??is increased by 3 when t is 1. 2 : the number of cycles ??is increased by 2 when t is 1. 3 : the number of cycles ??is increased by 1 when t is 1. 4 : the number of cycles ??is increased by 2 when branching has occurred. 5 : n, v, and z flags are invalid in decimal operation mode. 3 35 fd 4 ed 2 4 f5 f9 5 3 e1 6 2 f1 6 2 e9 2 2 0b + 20i 0f + 20i 21 52 e5 3 2 38 f8 78 32 2 2 2 2 1 1 1 1 42 aa a8 ba 8a 9a 98 c2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 95 94 5 5 2 2 96 52 8d 8e 8c 5 5 5 3 3 3 9d639963 81 7 2 91 7 2 n v 1 1 1 z c 1
3886 group user? manual 3.7 machine instructions
3886 group user? manual 3-87 appendix 3.8 list of instruction code 3.8 list of instruction code d 7 ?d 4 d 3 ?d 0 hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0 brk bpl jsr abs bmi rti bvc rts bvs bra bcc ldy imm bcs cpy imm bne cpx imm beq 0001 1 ora ind, x ora ind, y and ind, x and ind, y eor ind, x eor ind, y adc ind, x adc ind, y sta ind, x sta ind, y lda ind, x lda ind, y cmp ind, x cmp ind, y sbc ind, x sbc ind, y 0010 2 jsr zp, ind clt jsr sp set stp mul zp, x rrf zp ldx imm jmp zp, ind wit div zp, x 0011 3 bbs 0, a bbc 0, a bbs 1, a bbc 1, a bbs 2, a bbc 2, a bbs 3, a bbc 3, a bbs 4, a bbc 4, a bbs 5, a bbc 5, a bbs 6, a bbc 6, a bbs 7, a bbc 7, a 0100 4 bit zp com zp tst zp sty zp sty zp, x ldy zp ldy zp, x cpy zp cpx zp 0101 5 ora zp ora zp, x and zp and zp, x eor zp eor zp, x adc zp adc zp, x sta zp sta zp, x lda zp lda zp, x cmp zp cmp zp, x sbc zp sbc zp, x 0110 6 asl zp asl zp, x rol zp rol zp, x lsr zp lsr zp, x ror zp ror zp, x stx zp stx zp, y ldx zp ldx zp, y dec zp dec zp, x inc zp inc zp, x 0111 7 bbs 0, zp bbc 0, zp bbs 1, zp bbc 1, zp bbs 2, zp bbc 2, zp bbs 3, zp bbc 3, zp bbs 4, zp bbc 4, zp bbs 5, zp bbc 5, zp bbs 6, zp bbc 6, zp bbs 7, zp bbc 7, zp 1000 8 php clc plp sec pha cli pla sei dey tya tay clv iny cld inx sed 1001 9 ora imm ora abs, y and imm and abs, y eor imm eor abs, y adc imm adc abs, y sta abs, y lda imm lda abs, y cmp imm cmp abs, y sbc imm sbc abs, y 1010 a asl a dec a rol a inc a lsr a ror a txa txs tax tsx dex nop 1011 b seb 0, a clb 0, a seb 1, a clb 1, a seb 2, a clb 2, a seb 3, a clb 3, a seb 4, a clb 4, a seb 5, a clb 5, a seb 6, a clb 6, a seb 7, a clb 7, a 1100 c bit abs ldm zp jmp abs jmp ind sty abs ldy abs ldy abs, x cpy abs cpx abs 1101 d ora abs ora abs, x and abs and abs, x eor abs eor abs, x adc abs adc abs, x sta abs sta abs, x lda abs lda abs, x cmp abs cmp abs, x sbc abs sbc abs, x 1 110 e asl abs asl abs, x rol abs rol abs, x lsr abs lsr abs, x ror abs ror abs, x stx abs ldx abs ldx abs, y dec abs dec abs, x inc abs inc abs, x 1111 f seb 0, zp clb 0, zp seb 1, zp clb 1, zp seb 2, zp clb 2, zp seb 3, zp clb 3, zp seb 4, zp clb 4, zp seb 5, zp clb 5, zp seb 6, zp clb 6, zp seb 7, zp clb 7, zp : 3-byte instruction : 2-byte instruction : 1-byte instruction
3886 group user? manual 3.9 sfr memory map 3.9 sfr memory map 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 s e r i a l i / o 2 r e g i s t e r ( s i o 2 ) p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( p 5 d ) p o r t p 6 ( p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) p o r t p 7 ( p 7 ) p o r t p 7 d i r e c t i o n r e g i s t e r ( p 7 d ) p o r t p 8 ( p 8 ) / p o r t p 4 i n p u t r e g i s t e r ( p 4 i ) t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r ( t b / r b ) s e r i a l i / o 1 s t a t u s r e g i s t e r ( s i o 1 s t s ) s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) b a u d r a t e g e n e r a t o r ( b r g ) s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 ) p r e s c a l e r y ( p r e y ) t i m e r y ( t y ) a d / d a c o n t r o l r e g i s t e r ( a d c o n ) d - a 1 c o n v e r s i o n r e g i s t e r ( d a 1 ) d - a 2 c o n v e r s i o n r e g i s t e r ( d a 2 ) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) p r e s c a l e r 1 2 ( p r e 1 2 ) t i m e r 2 ( t 2 ) p r e s c a l e r x ( p r e x ) t i m e r x ( t x ) t i m e r 1 ( t 1 ) t i m e r x y m o d e r e g i s t e r ( t m ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c a d d r e s s r e g i s t e r ( s 0 d ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r ( s 2 d ) d a t a b a s b u f f e r r e g i s t e r 0 ( d b b 0 ) d a t a b a s b u f f e r s t a t u s r e g i s t e r 0 ( d b b s t s 0 ) d a t a b a s b u f f e r c o n t r o l r e g i s t e r ( d b b c o n ) d a t a b a s b u f f e r r e g i s t e r 1 ( d b b 1 ) d a t a b a s b u f f e r s t a t u s r e g i s t e r 1 ( d b b s t s 1 ) c o m p a r a t o r d a t a r e g i s t e r ( c m p d ) p o r t c o n t r o l r e g i s t e r 1 ( p c t l 1 ) p o r t c o n t r o l r e g i s t e r 2 ( p c t l 2 ) p w m 0 h r e g i s t e r ( p w m 0 h ) p w m 0 l r e g i s t e r ( p w m 0 l ) p w m 1 h r e g i s t e r ( p w m 1 h ) p w m 1 l r e g i s t e r ( p w m 1 l ) a - d c o n v e r s i o n r e g i s t e r 2 ( a d 2 ) i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( i n t s e l ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n ) 0ffe 16 0fff 16 f l a s h c o m m a n d r e g i s t e r ( f c m d ) f l a s h m e m o r y c o n t r o l r e g i s t e r ( f c o n ) (note) (note) note: flash memory version only p o r t p 8 d i r e c t i o n r e g i s t e r ( p 8 d ) / p o r t p 7 i n p u t r e g i s t e r ( p 7 i )
3886 group user s manual 3-89 appendix 3.10 pin configurations 3.10 pin configurations fig. 3.10.1 m3886 7m8a-xxxhp, m3886 7e8ahp pin configuration pin configuration (top view) fig. 3.10.2 m3886 7e8afs pin configuration pin configuration (top view) 21 2 2 2 3 24 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p3 0 /pwm 0 0 p 3 1 / p w m 1 0 p 6 2 / a n 2 p 6 1 / a n 1 p 4 4 / r x d p 4 3 / i n t 1 / o b f 0 1 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p 6 6 / a n 6 a v s s p 6 7 / a n 7 v r e f v c c p8 0 /dq 0 p8 1 /dq 1 p8 2 /dq 2 p8 3 /dq 3 p8 4 /dq 4 p8 5 /dq 5 p8 6 /dq 6 p8 7 /dq 7 p4 2 /int 0 /obf 0 0 c n v s s x i n x o u t v s s r e s e t p 4 0 / x c o u t p 4 1 / x c i n p 1 6 / a d 1 4 p1 7 /ad 15 p 2 6 / d b 6 p 2 5 / d b 5 p 2 4 / d b 4 p 2 3 / d b 3 p 2 2 / d b 2 p 2 1 / d b 1 p2 0 /db 0 p 3 4 / p 3 5 / s y n c p 0 0 / p 3 r e f / a d 0 p 0 4 / a d 4 p 0 5 / a d 5 p 0 6 / a d 6 p 0 7 / a d 7 p 1 1 / a d 9 p 1 2 / a d 1 0 p 1 3 / a d 1 1 p 1 4 / a d 1 2 p 1 5 / a d 1 3 p 1 0 / a d 8 p 0 1 / a d 1 p 0 2 / a d 2 p 3 2 / o n w p 3 3 / r e s e t o u t p 3 6 / w r p 3 7 / r d p 0 3 / a d 3 p 2 7 / d b 7 p 6 0 / a n 0 p 7 7 / s c l p 7 6 / s d a p 7 5 / i n t 4 1 p 7 4 / i n t 3 1 p 7 2 / s c l k 2 p 7 1 / s o u t 2 p 7 0 / s i n 2 p 5 7 / d a 2 / p w m 1 1 p 5 0 / a 0 p 4 5 / t x d p 7 3 / s r d y 2 / i n t 2 1 p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 6 / d a 1 / p w m 0 1 p 4 7 / s r d y 1 / s 1 p 5 2 / i n t 3 0 / r p 5 3 / i n t 4 0 / w p 5 1 / i n t 2 0 / s 0 p 4 6 / s c l k 1 / o b f 1 0 1 2 3 4 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 6 m3886 7m8a-xxxhp m3886 7e8ahp v pp 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 p 3 0 / p w m 0 0 p 3 1 / p w m 1 0 p 3 4 / p 3 5 / s y n c p 0 0 / p 3 r e f / a d 0 p 0 3 / a d 3 p 0 4 / a d 4 p 0 5 / a d 5 p 0 6 / a d 6 p 0 7 / a d 7 p 1 1 / a d 9 p 1 2 / a d 1 0 p 1 3 / a d 1 1 p 1 4 / a d 1 2 p 1 5 / a d 1 3 p 1 6 / a d 1 4 p 1 7 / a d 1 5 p 6 2 / a n 2 p 6 1 / a n 1 p 6 0 / a n 0 p 7 7 / s c l p 7 6 / s d a p 7 5 / i n t 4 1 p 7 4 / i n t 3 1 p 7 2 / s c l k 2 p 7 1 / s o u t 2 p 7 0 / s i n 2 p 5 7 / d a 2 / p w m 1 1 p 5 0 / a 0 p 4 6 / s c l k 1 / o b f 1 0 p 4 5 / t x d p 4 4 / r x d p 4 3 / i n t 1 / o b f 0 1 p 6 6 / a n 6 p 6 7 / a n 7 a v s s v r e f v c c p 8 0 / d q 0 p 8 1 / d q 1 p 8 2 / d q 2 p 8 3 / d q 3 p 8 4 / d q 4 p 8 5 / d q 5 p 8 6 / d q 6 p 8 7 / d q 7 p 4 2 / i n t 0 / o b f 0 0 c n v s s x in x o u t v ss p 2 7 / d b 7 p2 6 /db 6 p2 5 /db 5 p2 4 /db 4 p2 3 /db 3 p2 2 /db 2 p2 1 /db 1 p 2 0 / d b 0 rese t p 7 3 / s r d y 2 / i n t 2 1 p 5 1 / i n t 2 0 / s 0 p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 3 / i n t 4 0 / w p 5 2 / i n t 3 0 / r p 5 6 / d a 1 / p w m 0 1 p 1 0 / a d 8 p 0 1 / a d 1 p 0 2 / a d 2 p 4 7 / s r d y 1 / s 1 p 3 2 / o n w p 3 3 / r e s e t o u t p 3 6 / w r p 3 7 / r d p4 0 /x cou t p4 1 /x cin p 6 5 / a n 5 p 6 3 / a n 3 p 6 4 / a n 4 m 3 8 8 6 7 e 8 a f s v p p package type : 80d0 note: the pin number and the position of the function pin may change by the kind of package. package type : 80p6q-a : prom version note: the pin number and the position of the function pin may change by the kind of package. : prom version
3886 group user s manual 3.10 pin configurations fig. 3.10.3 m3886 9mfa-xxxgp/hp, m3886 9ffagp/hp pin configuration pin configuration (top view) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p3 0 /pwm 00 p3 1 /pwm 10 p6 2 /an 2 p6 1 /an 1 p4 4 /r x d p4 3 /int 1 /obf 01 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 av ss p6 7 /an 7 v ref v cc p8 0 /dq 0 p8 1 /dq 1 p8 2 /dq 2 p8 3 /dq 3 p8 4 /dq 4 p8 5 /dq 5 p8 6 /dq 6 p8 7 /dq 7 p4 2 /int 0 /obf 00 cnv ss x in x out v ss reset p4 0 /x cout p4 1 /x cin p1 6 p1 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 p3 4 p3 5 p0 0 /p3 ref p0 4 p0 5 p0 6 p0 7 p1 1 p1 2 p1 3 p1 4 p1 5 p1 0 p0 1 p0 2 p3 2 p3 3 p3 6 p3 7 p0 3 p2 7 p6 0 /an 0 p7 7 /s cl p7 6 /s da p7 5 /int 41 p7 4 /int 31 p7 2 /s clk2 p7 1 /s out2 p7 0 /s in2 p5 7 /da 2 /pwm 11 p5 0 /a 0 p4 5 /t x d p7 3 /s rdy2 /int 21 p5 5 /cntr 1 p5 4 /cntr 0 p5 6 /da 1 /pwm 01 p4 7 /s rdy1 /s 1 p5 2 /int 30 /r p5 3 /int 40 /w p5 1 /int 20 /s 0 p4 6 /s clk1 /obf 10 1 2 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 m3886 9mfa-xxxgp/hp m3886 9ffagp/hp v pp note: the pin number and the position of the function pin may change by the kind of package. : flash memory version package type : 80p6s-a/80p6q-a
3886 group sep. second edition 2000 editioned by committee of editing of mitsubishi semiconductor user? manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?000 mitsubishi electric corporation
3886 group ?2000 mitsubishi electric corporation. new publication, effective sep. 2000. specifications subject to change without notice.
